UCIe

Cadence and TSMC Collaborate on Wide-Ranging Innovations to Transform System and Semiconductor Design

Retrieved on: 
Wednesday, April 24, 2024
Automotive Manufacturing, Aerospace, Technology, Manufacturing, Semiconductor, Telecommunications, Software, Mobile, Wireless, 5G, Hardware, Electronic Design Automation, Spectre, EMX, TSMC, IP, Architecture, UCIe, AI, SOC, PCI Express, Certification, Silicon, CDNS, 3D, Cadence Design Systems, PDK, Automation, App Store (iOS/iPadOS), SVP, GDDR6, Simulation, EDA, GM, Schematic, LPDDR5, RF, DDR5, PPA, Virtuoso, D2D, EM, Video game

Cadence’s digital solutions are certified for TSMC N2 design flow, including Innovus™ Implementation System, Quantus™ Extraction Solution, Quantus Field Solver, Tempus™ Timing Signoff and ECO Solution, Pegasus™ Verification System, Liberate™ characterization, and the Voltus™ IC Power Integrity Solution.

Key Points: 
  • Cadence’s digital solutions are certified for TSMC N2 design flow, including Innovus™ Implementation System, Quantus™ Extraction Solution, Quantus Field Solver, Tempus™ Timing Signoff and ECO Solution, Pegasus™ Verification System, Liberate™ characterization, and the Voltus™ IC Power Integrity Solution.
  • Cadence and TSMC are collaborating on AI-driven Cadence solutions to enable an AI-assisted design flow for productivity and optimization of PPA results.
  • All have been enhanced for managing corner simulations, statistical analyses, design centering, and circuit optimization, which are now common with advanced nodes.
  • Cadence unveils a new silicon photonics flow to support TSMC’s Compact Universal Photonic Engine (COUPE) technology: Cadence and TSMC collaborate to develop a design flow for the COUPE 3D photonics process that features the Cadence Integrity 3D-IC platform.

Synopsys Accelerates Next-Level Chip Innovation on TSMC Advanced Processes

Retrieved on: 
Wednesday, April 24, 2024
Interface, TSMC, IP, N16, UCIe, AI, PCI Express, LPDDR, OIP, Silicon, Socs, MIPI, Engineering, Compiler, EDA, RF, DDR5, SNPS, PPA, USB, Semiconductor

SUNNYVALE, Calif., April 24, 2024 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) today announced broad EDA and IP collaborations with TSMC for advanced node designs and have been deployed across a range of AI, high-performance computing, and mobile designs. Among the newest collaborations is a co-optimized Photonic IC flow, addressing the application of silicon photonics technology in the quest for better power, performance, and transistor density. Synopsys also noted the industry's confidence in its digital and analog design flows, production-ready for TSMC N3/N3P and N2 process technologies. The two companies are collaborating on next-generation AI-driven flows, including Synopsys DSO.ai™, for design productivity and optimization. In addition, Synopsys is developing a broad portfolio of Foundation and Interface IP on TSMC N2/N2P. In a related announcement today, Keysight, Synopsys, and Ansys introduced a new integrated radio frequency (RF) design migration flow from TSMC's N16 process to its N6RF+ technology.

Key Points: 
  • Synopsys also noted the industry's confidence in its digital and analog design flows, production-ready for TSMC N3/N3P and N2 process technologies.
  • In addition, Synopsys is developing a broad portfolio of Foundation and Interface IP on TSMC N2/N2P.
  • A new flow is available for TSMC N5 to N3E migration, adding to Synopsys' established flows for TSMC N4P to N3E and N3E to N2 processes.
  • Synopsys IP for advanced TSMC processes has been adopted by dozens of leading companies to accelerate their development time.

Avicena Announces Scalable Sub-pJ/bit LightBundle™ Chiplet Interconnect with 10m Reach

Retrieved on: 
Monday, March 25, 2024
Semiconductor, Technology, Mobile, Wireless, Software, 5G, Artificial Intelligence, BOW, HBM, ICS, IO, GPU, Memory, HPC, AI, High Bandwidth Memory, Rump, Graphics processing unit, Scalability, Booth, ChatGPT, Artificial intelligence, Multimedia, MicroLED, UCIe, Video game

Avicena, headquartered in Sunnyvale, CA, is announcing its new scalable LightBundle chiplet interconnect at OFC 2024 in San Diego, CA ( https://www.ofcconference.org/en-us/home/ ).

Key Points: 
  • Avicena, headquartered in Sunnyvale, CA, is announcing its new scalable LightBundle chiplet interconnect at OFC 2024 in San Diego, CA ( https://www.ofcconference.org/en-us/home/ ).
  • The chiplet interconnect extends ultra-high density die-to-die (D2D) connections up to 10m at multi-Tbps/mm shoreline bandwidth density and class leading sub-pJ/bit energy efficiency.
  • The LightBundle chiplet interconnect extends HBM and other ultra-high performance D2D connections up to 10m while dissipating
  • “At Avicena, we are excited to announce our ultra-low power scalable chiplet interconnect based on our LightBundle platform,” says Bardia Pezeshki, Founder and CEO of Avicena.

Alphawave Semi Demonstrates 3nm Silicon-Proven 24Gbps Universal Chiplet ExpressTM (UCIeTM) Subsystem for High-Performance AI Infrastructure

Retrieved on: 
Tuesday, March 12, 2024
Networks, Internet, Hardware, Artificial Intelligence, Data Management, Technology, IOT (Internet of Things), Semiconductor, HBM, Info, Innovation, Integration, CHI, CXL, CXS, PCI Express, Multi, Marketing, OIP, Semi, Ecosystem, PHY, Multimedia, Computation, UCIe, TSMC, Silicon, Video game

This new silicon-proven Universal Chiplet Interconnect Express (UCIeTM) subsystem expands Alphawave Semi’s portfolio and leadership in connectivity silicon.

Key Points: 
  • This new silicon-proven Universal Chiplet Interconnect Express (UCIeTM) subsystem expands Alphawave Semi’s portfolio and leadership in connectivity silicon.
  • It paves the way for a robust, open chiplet ecosystem that accelerates connectivity and compute for high-performance AI systems.
  • An industry-first live demo of Alphawave Semi’s 24Gbps UCIe silicon platform on the TSMC 3nm process was recently unveiled at the Chiplet Summit in Santa Clara, CA.
  • View the full release here: https://www.businesswire.com/news/home/20240311461384/en/
    Alphawave Semi 24Gbps UCIe 3nm silicon platform (Graphic: Business Wire)
    Alphawave Semi’s 3nm UCIe complete PHY + Controller subsystem is capable of 24Gbps data rates, delivering high bandwidth density at extremely low power and low latency.

Synopsys Announces New AI-Driven EDA, IP and Systems Design Solutions At SNUG Silicon Valley

Retrieved on: 
Wednesday, March 20, 2024
Cloud, Momentum, CVP, Socs, History, IP, PUF, Microsoft, 4X, Synthetic media, Intel, Webcast, 3D, Software, Ghazi, HAV, Compiler, PPA, Intrinsic and extrinsic properties, RTL, EDA, News, Acquisition, AI, Field-programmable gate array, Architecture, Samsung, AMD, Santa Clara Convention Center, Engineering, UCIe, Stunning, Ecosystem, EP2, SNPS, Generative, TSMC, Video game

SUNNYVALE, Calif., March 20, 2024 /PRNewswire/ -- Today Synopsys, Inc. (Nasdaq: SNPS) kicked off its annual flagship Synopsys User Group (SNUG) conference in Silicon Valley at the Santa Clara Convention Center with a keynote presentation by Synopsys president and CEO Sassine Ghazi. Ghazi discussed the unprecedented innovation opportunities and challenges that technology R&D teams face in this era of pervasive intelligence. He also announced new EDA and IP solutions aimed at maximizing the capabilities of the global technology engineering teams, from silicon to systems, that Synopsys serves.

Key Points: 
  • (Nasdaq: SNPS ) kicked off its annual flagship Synopsys User Group (SNUG) conference in Silicon Valley at the Santa Clara Convention Center with a keynote presentation by Synopsys president and CEO Sassine Ghazi.
  • He also announced new EDA and IP solutions aimed at maximizing the capabilities of the global technology engineering teams, from silicon to systems, that Synopsys serves.
  • The company plans to discuss its growing design IP business during this afternoon's investor meeting, which is co-located with SNUG Silicon Valley.
  • Happening March 20 and 21 in Santa Clara, Calif., SNUG Silicon Valley gathers the global Synopsys design community to discuss technology advancements, challenges, strategic collaborations, and business opportunities.

Global and China Automotive RISC-V Chip Industry Research Report 2024: Customized Chips May Become the Future Trend, and RISC-V will Challenge ARM

Retrieved on: 
Friday, March 15, 2024
ISA, Research, Certification, IO, SOC, Memory, Veyron, Qualcomm, Computing, Threshold, Electronics, RISC, Internet, IATF, ARM, IDE, Software, Architecture, IP, SiFive, Ecosystem, X86, NXP, Patent, Family, CPU, Economics, UCIe, ICT, Video game

DUBLIN, March 14, 2024 /PRNewswire/ -- The "Automotive RISC-V Chip Industry Research Report, 2024" report has been added to ResearchAndMarkets.com's offering.

Key Points: 
  • DUBLIN, March 14, 2024 /PRNewswire/ -- The "Automotive RISC-V Chip Industry Research Report, 2024" report has been added to ResearchAndMarkets.com's offering.
  • In contrast, ARM and X86 are not only complicated in instruction set development, but also difficult to obtain authorization to modify instruction sets.
  • In terms of customization, it enables designers to create thousands of potential customized processors, thus speeding up the time to market.
  • In the past, automotive chips were mainly based on ARM or private architectures of some European chip companies.

Synopsys and Intel Foundry Accelerate Advanced Chip Designs with Synopsys IP and Certified EDA Flows for Intel 18A Process

Retrieved on: 
Wednesday, February 21, 2024
Compiler, Intel, Socs, Silicon, Family, GM, PDK, Interface, EDA, Multigate device, SNPS, Ecosystem, IP, UCIe, Semiconductor

SUNNYVALE, Calif., Feb. 21, 2024 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) today announced its AI-driven digital and analog design flows are certified by Intel Foundry for the Intel 18A process. In addition, through integration of high-quality Synopsys Foundation IP and Interface IP tuned for Intel Foundry technology, mutual customers can confidently design and deliver differentiated chips using advanced Intel Foundry technologies. With its certified EDA flows, multi-die system solution, and comprehensive IP portfolio in development for the Intel 18A process, Synopsys is helping designers accelerate the development of advanced high-performance designs. Today's announcement is being made at the Intel Foundry Direct Connect 2024 event, where Aart de Geus, Synopsys executive chair and founder, will present "Catalyzing SysMoore Together."

Key Points: 
  • (Nasdaq: SNPS ) today announced its AI-driven digital and analog design flows are certified by Intel Foundry for the Intel 18A process.
  • With its certified EDA flows, multi-die system solution, and comprehensive IP portfolio in development for the Intel 18A process, Synopsys is helping designers accelerate the development of advanced high-performance designs.
  • To realize the advantages of the Intel 18A process and to bring differentiated products to market, Intel Foundry customers can integrate a comprehensive Synopsys IP portfolio built for Intel advanced process technologies.
  • Synopsys and Intel Foundry are also driving multi-die systems forward with Synopsys 3DIC Compiler platform and Intel's advanced foundry processes.

Tenstorrent Selects Blue Cheetah Chiplet Interconnect IP For Its AI and RISC-V Solutions

Retrieved on: 
Tuesday, February 6, 2024
CHI, National Oceanography Centre, Southampton, AXI, ACE, Bow, OCP, PHY, UCIe

SUNNYVALE, Calif., Feb. 6, 2024 /PRNewswire/ -- Tenstorrent and Blue Cheetah Analog Design today announced that Tenstorrent has licensed Blue Cheetah's die-to-die interconnect IP for its AI and RISC-V chiplet solutions.

Key Points: 
  • SUNNYVALE, Calif., Feb. 6, 2024 /PRNewswire/ -- Tenstorrent and Blue Cheetah Analog Design today announced that Tenstorrent has licensed Blue Cheetah's die-to-die interconnect IP for its AI and RISC-V chiplet solutions.
  • By selecting Blue Cheetah, Tenstorrent aims to accelerate its own as well as its customers' and partners' development of chiplet-based AI and RISC-V solutions.
  • Blue Cheetah currently provides its chiplet interconnect IP solutions in 4 nm, 5nm, 7nm, 12nm, and 16nm process technologies.
  • "Tenstorrent delivers highly customized, high-performance AI and RISC-V chiplet solutions tailored to specific workloads and applications," said Elad Alon, CEO of Blue Cheetah.

Keysight Introduces Chiplet PHY Designer for Simulating D2D to D2D PHY IP Supporting the UCIe™ Standard

Retrieved on: 
Wednesday, January 24, 2024
Technology, Hardware, Electronic Design Automation, Semiconductor, HBM3, Senior, D2D, Chiplet, BER, EDA, LPDDR5, SerDes, Multimedia, IBIS, Ecosystem, VTF, 3D, DDR5, Commerce, UCIe, JEDEC, Printed circuit board

View the full release here: https://www.businesswire.com/news/home/20240124811619/en/

Key Points: 
  • View the full release here: https://www.businesswire.com/news/home/20240124811619/en/
    Chiplet PHY Designer simulates the UCIe specification for D2D physical layer interconnect.
  • (Graphic: Business Wire)
    UCIe is emerging as the leading chiplet interconnect specification in the semiconductor industry.
  • Chiplet PHY Designer simplifies the electrical simulation process for large die-die electrical connectivity, such as UCIe.
  • Chiplet PHY Designer accelerates validation of chiplet subsystems, from one D2D PHY through interconnect channels to another D2D PHY, much earlier in the design cycle.

Keysight Spotlights Solutions Enabling Better AI Infrastructure at DesignCon 2024

Retrieved on: 
Tuesday, January 16, 2024
Technology, Telecommunications, Software, Networks, Internet, Hardware, Electronic Design Automation, Data Management, Consumer Electronics, Artificial Intelligence, Noise, PCI Express, Architecture, PHY, USB4, DRAM, SerDes, Booth, AI, Ecosystem, CXL, Return loss, Analyser, DDR5, UCIe, PCI

Keysight will present the following sessions at DesignCon 2024 : Keysight Education Forum (KEF), technical presentations/papers, and more.

Key Points: 
  • Keysight will present the following sessions at DesignCon 2024 : Keysight Education Forum (KEF), technical presentations/papers, and more.
  • Enabling PCIe 7.0 Technology – PCIe architecture provides a robust high-bandwidth interconnect solution for attaching compute chips and network devices used in AI / ML applications.
  • This will demonstrate Keysight’s solutions that can be used to enable the testing of PCI Express 7.0 transmitter and receiver technologies.
  • This demonstration will highlight vector network analysis and time domain reflectometry measurement solutions Keysight has developed to address these new challenges.