Compiler

Synopsys Announces New AI-Driven EDA, IP and Systems Design Solutions At SNUG Silicon Valley

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Wednesday, March 20, 2024
Cloud, Momentum, CVP, Socs, History, IP, PUF, Microsoft, 4X, Synthetic media, Intel, Webcast, 3D, Software, Ghazi, HAV, Compiler, PPA, Intrinsic and extrinsic properties, RTL, EDA, News, Acquisition, AI, Field-programmable gate array, Architecture, Samsung, AMD, Santa Clara Convention Center, Engineering, UCIe, Stunning, Ecosystem, EP2, SNPS, Generative, TSMC, Video game

SUNNYVALE, Calif., March 20, 2024 /PRNewswire/ -- Today Synopsys, Inc. (Nasdaq: SNPS) kicked off its annual flagship Synopsys User Group (SNUG) conference in Silicon Valley at the Santa Clara Convention Center with a keynote presentation by Synopsys president and CEO Sassine Ghazi. Ghazi discussed the unprecedented innovation opportunities and challenges that technology R&D teams face in this era of pervasive intelligence. He also announced new EDA and IP solutions aimed at maximizing the capabilities of the global technology engineering teams, from silicon to systems, that Synopsys serves.

Key Points: 
  • (Nasdaq: SNPS ) kicked off its annual flagship Synopsys User Group (SNUG) conference in Silicon Valley at the Santa Clara Convention Center with a keynote presentation by Synopsys president and CEO Sassine Ghazi.
  • He also announced new EDA and IP solutions aimed at maximizing the capabilities of the global technology engineering teams, from silicon to systems, that Synopsys serves.
  • The company plans to discuss its growing design IP business during this afternoon's investor meeting, which is co-located with SNUG Silicon Valley.
  • Happening March 20 and 21 in Santa Clara, Calif., SNUG Silicon Valley gathers the global Synopsys design community to discuss technology advancements, challenges, strategic collaborations, and business opportunities.

Newgen Recognized in an Analyst Report on Accounts Payable Invoice Automation

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Monday, March 11, 2024
Organization, ERP, Invoice, OCR, CFOS, Compiler, Organizing, Centralisation, SLA, Online shopping

NOIDA, India, March 11, 2024 /PRNewswire/ -- Newgen Software, a global provider of low code digital transformation platform, announced that Newgen's accounts payable solution is recognized among 33 notable vendors in Forrester's 'The Accounts Payable Invoice Automation Landscape, Q4 2023' report.

Key Points: 
  • NOIDA, India, March 11, 2024 /PRNewswire/ -- Newgen Software, a global provider of low code digital transformation platform, announced that Newgen's accounts payable solution is recognized among 33 notable vendors in Forrester's 'The Accounts Payable Invoice Automation Landscape, Q4 2023' report.
  • This report assists CFOs, controllers, business leaders, and finance and payment professionals in understanding the value that can be expected from an APIA vendor and identifying the most effective and cost-efficient invoice automation solution for their business.
  • "At Newgen, we are committed to transforming the finance and accounts function by understanding the unique needs and expectations of finance, vendors, and other stakeholders.
  • To access the complete report, read Forrester's 'The Accounts Payable Invoice Automation Landscape, Q4 2023' report.

INDUSTRY LEADING PPA DSP AVAILABLE FOR ALL EXISTING EFLX EFPGA

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Wednesday, March 6, 2024
Compiler, Simulink, TPU, Verilog, Silicon, Macs, Complex, FFT, IP, DSP, FPGA

MOUNTAIN VIEW, Calif., March 6, 2024 /PRNewswire/ -- Flex Logix® Technologies, Inc., the leading supplier of embedded FPGA (eFPGA) IP and reconfigurable DSP/AI solutions, announced today that InferX DSP is in development for use with existing EFLX eFPGA from 40nm to 7nm.

Key Points: 
  • MOUNTAIN VIEW, Calif., March 6, 2024 /PRNewswire/ -- Flex Logix® Technologies, Inc. , the leading supplier of embedded FPGA (eFPGA) IP and reconfigurable DSP/AI solutions, announced today that InferX DSP is in development for use with existing EFLX eFPGA from 40nm to 7nm.
  • One, two, four, eight or 16 TPUs can be controlled by existing EFLX eFPGA from 40nm to 7nm.
  • "InferX with existing EFLX eFPGA allows us to deliver much higher DSP throughput at much lower cost than eFPGA with MACs.
  • Benchmarks are available for all of the process nodes we have silicon for now: 40, 28, 22, 16, 12, 7nm.

Synopsys and Intel Foundry Accelerate Advanced Chip Designs with Synopsys IP and Certified EDA Flows for Intel 18A Process

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Wednesday, February 21, 2024
Compiler, Intel, Socs, Silicon, Family, GM, PDK, Interface, EDA, Multigate device, SNPS, Ecosystem, IP, UCIe, Semiconductor

SUNNYVALE, Calif., Feb. 21, 2024 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) today announced its AI-driven digital and analog design flows are certified by Intel Foundry for the Intel 18A process. In addition, through integration of high-quality Synopsys Foundation IP and Interface IP tuned for Intel Foundry technology, mutual customers can confidently design and deliver differentiated chips using advanced Intel Foundry technologies. With its certified EDA flows, multi-die system solution, and comprehensive IP portfolio in development for the Intel 18A process, Synopsys is helping designers accelerate the development of advanced high-performance designs. Today's announcement is being made at the Intel Foundry Direct Connect 2024 event, where Aart de Geus, Synopsys executive chair and founder, will present "Catalyzing SysMoore Together."

Key Points: 
  • (Nasdaq: SNPS ) today announced its AI-driven digital and analog design flows are certified by Intel Foundry for the Intel 18A process.
  • With its certified EDA flows, multi-die system solution, and comprehensive IP portfolio in development for the Intel 18A process, Synopsys is helping designers accelerate the development of advanced high-performance designs.
  • To realize the advantages of the Intel 18A process and to bring differentiated products to market, Intel Foundry customers can integrate a comprehensive Synopsys IP portfolio built for Intel advanced process technologies.
  • Synopsys and Intel Foundry are also driving multi-die systems forward with Synopsys 3DIC Compiler platform and Intel's advanced foundry processes.

Rapid Silicon Leads the Way with First Complete Open-Source FPGA EDA Tool-Chain

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Tuesday, February 20, 2024
Logic analyzer, Compiler, LOS, JTAG, AI, IPS, University of Toronto, Silicon, GPL3, GUI, EDA, University, SDK, Field-programmable gate array, Electrical engineering, Raptor, Electricity, IP, FPGA, Video game

This marks a significant shift for Rapid Silicon, as it transitions from a hybrid model to a full open-source model, embracing a 100% open-source flow.

Key Points: 
  • This marks a significant shift for Rapid Silicon, as it transitions from a hybrid model to a full open-source model, embracing a 100% open-source flow.
  • The launch of Raptor Design Suite signifies a game-changing moment for the EDA industry, offering unparalleled accessibility and flexibility to designers worldwide.
  • With a comprehensive array of features, Raptor Design Suite empowers users with a complete end-to-end open-source tool flow.
  • "We are pleased to announce the Raptor Design Suite, the industry's first end-to-end 100% open-source FPGA SDK and Compiler," said Alain Dargelas, VP of Software at Rapid Silicon.

McKesson to Present at the 42nd Annual J.P. Morgan Healthcare Conference

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Tuesday, January 9, 2024
Medical Supplies, Health, Logistics, Supply Chain Management, Transport, Hospitals, General Health, Pharmaceutical, Northwestern University, MCK, Compiler, University, Committee on Finance, Kellogg School, Acquisition, Conference, McKesson Corporation, Audit committee, Management

McKesson Corporation (NYSE: MCK) will present at the 42nd Annual J.P. Morgan Healthcare Conference at the Westin St. Francis Hotel in San Francisco today at 9:45 AM PT (12:45 PM ET).

Key Points: 
  • McKesson Corporation (NYSE: MCK) will present at the 42nd Annual J.P. Morgan Healthcare Conference at the Westin St. Francis Hotel in San Francisco today at 9:45 AM PT (12:45 PM ET).
  • The audio webcast will be available live at McKesson’s Investor Relations website at investor.mckesson.com , along with the company’s slide presentation.
  • The McKesson board of directors has elected Kevin Ozan as director and member of the Audit Committee and Finance Committee, effective January 8, 2024.
  • On January 4, 2024, McKesson acquired Compile, a healthcare data platform that aggregates and integrates data from across the US healthcare system to characterize providers and their patient panels.

Complete MISRA C++ 2023 Support Empowers C++ Developers

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Wednesday, December 13, 2023
MISRA, ARM, Safety, EDG, Qualcomm Hexagon, Parasoft, GNU GCC, MISRA C, Collection, Risk, Clang, GNU, Visual Studio Code, CERT, IAR, Compiler, Satellite navigation device, Medical device, Risk management

MONROVIA, Calif., Dec. 13, 2023 /PRNewswire/ -- Parasoft introduces the latest release of C/C++test 2023.2, a transformative tool in C++ development. This update enables developers with a suite of new features, enhancements, and compliance tools, reforming the software development life cycle. With Parasoft C/C++test 2023.2, users have a solution that provides assurance that their C++17 code compliant to MISRA C++ 2023. Parasoft continuously provides complete enforcement of safety and security coding standards, such as complete support for MISRA C++ 2023.

Key Points: 
  • Complete support for MISRA C++ 2023: Parasoft's C/C++test 2023.2 release strengthens its position as a leader by ensuring comprehensive adherence to MISRA C++ 2023.
  • Parasoft continuously provides complete enforcement of safety and security coding standards, such as complete support for MISRA C++ 2023.
  • It guarantees complete support for MISRA C++ 2023, reflecting Parasoft's commitment to ensuring compliance and safety within C++17 code.
  • Contact Parasoft for a briefing on the release of Parasoft C/C++test 2023.3 with complete support of MISRA C++ 2023.

OpenHW Group Announces CORE-V CVA6 Platform Project for RISC-V Software Development & Testing

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Tuesday, November 7, 2023
Semiconductor, Hardware, Electronic Design Automation, Technology, Software, UCSB, Software engineering, SW, Assistant, FPGA, Platform, BSC, IDE, Environment, Princeton University, Compiler, Logic, SDK, Ecosystem, Xilinx, AWS, Safety, Amazon, Red Hat, Communication, Digilant, Memory, Silicon, Network on a chip, CI, Video game, Cryptocurrency, Ashling, Thales of Miletus

Today, at the RISC-V Summit, the OpenHW Group announced the multi-member CORE-V CVA6 Platform project .

Key Points: 
  • Today, at the RISC-V Summit, the OpenHW Group announced the multi-member CORE-V CVA6 Platform project .
  • The platform is an open-source FPGA-based software development and testing environment for RISC-V processors designed to provide a vendor-neutral environment for RISC-V software CI and testing that keeps pace with RISC-V standards.
  • We’re pleased to work with other industry leaders on the CORE-V CVA6 Platform project as we collectively work to make the platform an ideal location for RISC-V software testing and development,” stated Hugh Brock, Director, Software Engineering, Red Hat.
  • "As a leading contributor to the RISC-V evolution and leaders of the CVA6 core project within the OpenHW community, we believe the CORE-V CVA6 Platform will accelerate community efforts on RISC-V compliance and software development.

Mana.bio Advances AI-Based Lipid Nanoparticle (LNP) Platform to Accelerate "Programmable Drug Delivery" for RNA and Gene Therapies

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Tuesday, October 10, 2023
Nanomedicine, Data science, Doctor of Philosophy, Machine learning, Vaccine, Yogev, TEL, RNA, LNP, EBay, AI, MD, Organization, Therapy, Cardiology, Neurology, Twist, Wolf Foundation, Cystic fibrosis, Health, Department of Chemical Engineering, Imperial College London, Biotechnology, Medicine, General partnership, Beam Therapeutics, R, Artificial intelligence, Twist Bioscience, Bayer, MIT, CRISPR, Conditional sentence, Chemical engineering, Compiler, Chemical substance, Gene editing, MIT Technology Review, IPO, Tissue, Rising Star, Institution of Chemical Engineers, Nanotechnology, Young Innovation Leaders Fellowship, Pharmaceutical industry, Biogen, Pfizer, Technion – Israel Institute of Technology

Mana.bio's integrated experimental and machine learning platform enables the discovery of smarter, faster, more precise delivery formulations to unlock the field of nucleic acid-based and genetic medicines.

Key Points: 
  • Mana.bio's integrated experimental and machine learning platform enables the discovery of smarter, faster, more precise delivery formulations to unlock the field of nucleic acid-based and genetic medicines.
  • We are encouraged by our platform's early in vivo success and for its potential to deliver breakthrough therapies for a broad range of diseases."
  • RNA-based therapies and genetic medicines offer immense potential to transform approaches to vaccines, gene editing, gene therapy and more.
  • The limitations on delivery methods have severely restricted the full therapeutic promise of RNA, CRISPR and gene therapies.

Synopsys and TSMC Streamline Multi-Die System Complexity with Unified Exploration-to-Signoff Platform and Proven UCIe IP on TSMC N3E Process

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Wednesday, September 27, 2023
PHY, HBM3, IP, UCIe, SNPS, Compiler, TSMC, Architecture, Silicon, Extrusion, Semiconductor, Printed circuit board, Ansys, Synopsys

SUNNYVALE, Calif., Sept. 27, 2023 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) today announced it is extending its collaboration with TSMC to advance multi-die system designs with a comprehensive solution supporting the latest 3Dblox 2.0 standard and TSMC's 3DFabric™ technologies. The Synopsys Multi-Die System solution includes 3DIC Compiler, a unified exploration-to-signoff platform that delivers the highest levels of design efficiency for capacity and performance. In addition, Synopsys has achieved first-pass silicon success of its Universal Chiplet Interconnect Express (UCIe) IP on TSMC's leading N3E process for seamless die-to-die connectivity.

Key Points: 
  • Synopsys UCIe PHY IP, which achieved first-pass silicon success on TSMC N3E process, provides low-latency, low-power, and high-bandwidth die-to-die connectivity.
  • The combination of UCIe PHY IP and 3DIC Compiler optimizes multi-die system design for higher quality-of-results with minimal integration risk.
  • The Synopsys Multi-Die System solution includes 3DIC Compiler, a unified exploration-to-signoff platform that delivers the highest levels of design efficiency for capacity and performance.
  • Synopsys UCIe PHY IP on the TSMC N3E process and 3DIC Compiler are available now.