UCIe

Valens Semiconductor and Intel Foundry Services Announce Strategic Relationship for Next Generation A-PHY Product

Retrieved on: 
Monday, January 8, 2024
Architecture, Intel, Ecosystem, Family, VLN, HOD, Valens Semiconductor, MIPI, IP, UCIe, Electromagnetic compatibility, Safety, EMC, Senior, Semiconductor

HOD HASHARON, Israel, Jan. 8, 2024 /PRNewswire/ -- Today, Valens Semiconductor (NYSE:VLN) and Intel Foundry Services (IFS) announce that IFS will fabricate Valens Semiconductor's MIPI A-PHY chipsets using its advanced process nodes, aiming to address the robust demand in the market for this innovative connectivity solution. This collaboration furthers the strategic relationship between Valens and IFS that starts with the development of next generation of A-PHY in the automotive industry based on Intel leading-edge technology.

Key Points: 
  • This collaboration furthers the strategic relationship between Valens and IFS that starts with the development of next generation of A-PHY in the automotive industry based on Intel leading-edge technology.
  • Valens Semiconductor, a key contributor to the standard, was the first on the market to offer A-PHY-compliant chipsets with its VA7000 product family.
  • "Best-in-class products, like our A-PHY chipsets, require best-in-class processes – and that's exactly what we're getting through this collaboration with Intel Foundry Services" said Gideon Ben Zvi, CEO of Valens Semiconductor.
  • As part of this strategic collaboration, Valens Semiconductor will utilize Intel's leading edge process technology to produce its second generation of A-PHY chipsets.

Chiplet Summit Announces Its Initial Keynote Schedule With Emphasis on AI Applications

Retrieved on: 
Tuesday, January 2, 2024
Semiconductor, Apps, Applications, Technology, Software, Networks, Artificial Intelligence, Hardware, UCIe, Santa Clara Convention Center, Silicon, SNIA, AI, Memory, Engineering

The second annual Chiplet Summit, to occur on February 6-8 at the Santa Clara Convention Center, has now set its initial keynote schedule.

Key Points: 
  • The second annual Chiplet Summit, to occur on February 6-8 at the Santa Clara Convention Center, has now set its initial keynote schedule.
  • Speakers will be:
    Cliff Grossner and Bapi Vinnakota, Open Compute Project
    There will also be short talks by the UCIe Consortium, Silicon Catalyst, and SNIA.
  • Keynote topics will include AI solutions, design methods, memory, interfaces, new packaging methods, and the open chiplet economy.
  • Summit General Chair Chuck Sobey says, “At our keynotes, attendees hear what industry leaders are planning.

Untether AI Joins UCIe Consortium to Drive Chiplet Technology and Energy-Centric AI Acceleration

Retrieved on: 
Tuesday, November 28, 2023
Software, Networks, Internet, Hardware, Artificial Intelligence, Data Management, Technology, Semiconductor, Memory, Communication, Computing, Central processing unit, Acceleration, NOC, Graphics processing unit, UCIe, AI, Algorithm, Medical device, Video game

As the leader in energy-centric AI acceleration, Untether AI sees heterogeneous compute with die-to-die interconnect as the next logical step for energy-centric compute architectures.

Key Points: 
  • As the leader in energy-centric AI acceleration, Untether AI sees heterogeneous compute with die-to-die interconnect as the next logical step for energy-centric compute architectures.
  • "We are pleased to join the UCIe Consortium to advance the future of AI acceleration," said Arun Iyengar, CEO, Untether AI.
  • “By leveraging chiplet technology and UCIe's universal standards, Untether AI will deliver energy efficient AI acceleration chiplets to the market.
  • “Untether AI’s contribution will help showcase the benefits of UCIe, a low-power, high-speed, and open industry standard chiplet interface."

Ventana Introduces Veyron V2 -- World's Highest Performance Data Center-Class RISC-V Processor and Platform

Retrieved on: 
Tuesday, November 7, 2023
RISE, Chiplet, Economics, UCIe, Speech, Composable disaggregated infrastructure, SDK, Ecosystem, IO, Overalls, AI, Software development kit, IP, Veyron, Memory, Mobile phone, Cryptocurrency, Video game

CUPERTINO, Calif., Nov. 7, 2023 /PRNewswire/ -- Ventana Micro Systems Inc. today announced the second generation of its Veyron family of RISC-V processors. The new Veyron V2 is the highest performance RISC-V processor available today and is offered in the form of chiplets and IP.

Key Points: 
  • The new Veyron V2 is the highest performance RISC-V processor available today and is offered in the form of chiplets and IP.
  • Ventana Founder and CEO Balaji Baktha will share the details of Veyron V2 today during his keynote speech at the RISC-V Summit North America 2023 in Santa Clara, California.
  • This gain has been made possible through significant microarchitecture enhancements, superior high performance processor fabric architecture, enhanced cache hierarchy, and the addition of a high performance vector processor.
  • Ventana provides a Software Development Kit (SDK) which includes a comprehensive set of software building blocks already proven on Ventana's RISC-V platform.

Alphawave Semi Elevates Chiplet-Powered Silicon Platforms for AI Compute through Arm Total Design

Retrieved on: 
Tuesday, October 17, 2023
Electronic Design Automation, Semiconductor, Technology, Software, Artificial Intelligence, Internet, IP, Silicon, CSS, ARM Neoverse, AXI, PPA, Semi, GM, Computation, Memory, Total, Ecosystem, Socs, SVP, Synthetic media, LSE, UCIe, History, Dance, Video game

The integration of Arm Neoverse CSS onto the most advanced high-speed connectivity IP and chiplet-enabled custom silicon platforms from Alphawave Semi propels AI compute to new heights and paves the way for a new generation of SoCs tailored for hyperscaler and data infrastructure customers.

Key Points: 
  • The integration of Arm Neoverse CSS onto the most advanced high-speed connectivity IP and chiplet-enabled custom silicon platforms from Alphawave Semi propels AI compute to new heights and paves the way for a new generation of SoCs tailored for hyperscaler and data infrastructure customers.
  • Generative AI has fundamentally transformed data center compute and connectivity by creating a surge in demand for compute, memory bandwidth, I/O speeds, and energy efficiency.
  • “Arm Total Design represents another step forward in Alphawave Semi’s collaborative efforts in fostering innovation through a robust chiplet ecosystem."
  • “We are very excited to be part of Arm Total Design because it opens new opportunities for Alphawave Semi to deliver unprecedented levels of compute performance, flexibility, and scalability to our hyperscaler and data-infrastructure customers” said Mohit Gupta, SVP and GM, Custom Silicon and IP, Alphawave Semi.

Zero ASIC Democratizing Chip Making

Retrieved on: 
Tuesday, October 17, 2023
Silicon, 3D, RTL, ASIC, Chiplet, Gamer, COTS, 2D, IO, Robotics, Field-programmable gate array, UCIe, Catalog, Software, SOC, Application-specific integrated circuit, Semiconductor, Cryptocurrency

CAMBRIDGE, Ma., Oct. 17, 2023 /PRNewswire/ -- Zero ASIC, a semiconductor startup, today announced early access to its one-of-a-kind ChipMaker platform, demonstrating a number of world firsts:

Key Points: 
  • Our mission at Zero ASIC is to make ordering an ASIC as easy as ordering catalog parts from an electronics distributor."
  • Zero ASIC has delivered on the chiplet vision by by creating a platform that enables automated design, validation, and assembly of System-in-Packages from a catalog of known good chiplets.
  • To address these problems, Zero ASIC has developed eFabric, an active grid-like 3D interposer that improves die-to-die communication efficiency and composability.
  • Zero ASIC will be showing live demonstrations of the ChipMaker platform at the Open Compute Platform Summit (Open Chiplet Economy Center) October 17-19, in San Jose, CA.

Credo to Showcase Datacenter AI, Compute and CXL at OCP Global Summit in San Jose

Retrieved on: 
Monday, October 16, 2023
Technology, Venture Capital, Other Technology, Professional Services, Software, Networks, Internet, Hardware, Data Management, Multimedia, CXL, Business, World of McIntosh Experience Center, AI, Expo Hall, DriveNets, Meta, Rack, RDMA, AEC Routemaster, Synthetic media, UCIe, OCP, Credo, Instrumentation, Medical device, SerDes

Credo Technology Group Holding Ltd (“Credo”) (Nasdaq: CRDO), an innovator in providing secure, high-speed connectivity solutions that deliver improved power and energy-efficiency, is excited to announce its participation in the upcoming OCP Global Summit on October 17-19,2023 in San Jose, CA.

Key Points: 
  • Credo Technology Group Holding Ltd (“Credo”) (Nasdaq: CRDO), an innovator in providing secure, high-speed connectivity solutions that deliver improved power and energy-efficiency, is excited to announce its participation in the upcoming OCP Global Summit on October 17-19,2023 in San Jose, CA.
  • OCP provides Credo with a platform to showcase generative AI, general compute and operator focused connectivity solutions.
  • View the full release here: https://www.businesswire.com/news/home/20231016050756/en/
    The OCP Global Summit provides Credo with a platform to showcase our generative AI, general compute and operator focused connectivity solutions.
  • Credo invites all OCP Global Summit attendees to visit booth #B10 and the Rack and Power Experience Center and attend our presentations to learn more.

Advantest to Showcase Latest Semiconductor Test Solutions at the International Test Conference in Anaheim, California

Retrieved on: 
Monday, October 2, 2023
LBIST, SLT, MBIST, Advantest, IO, ATE, ATS, DUT, ARTS, ICS, UCIe, DUT board, Test, ACS, SLM, Socs, SCAN, Diagnosis, ITC, Ecosystem, Conference, VI, TSE, Printed circuit board, Synopsys

TOKYO, Oct. 02, 2023 (GLOBE NEWSWIRE) -- Leading semiconductor test equipment supplier Advantest Corporation (TSE: 6857) will feature its latest test solutions for advanced ICs at the 2023 International Test Conference (ITC) on Oct. 8-13 at the Disneyland Convention Center in Anaheim, California.

Key Points: 
  • TOKYO, Oct. 02, 2023 (GLOBE NEWSWIRE) -- Leading semiconductor test equipment supplier Advantest Corporation (TSE: 6857) will feature its latest test solutions for advanced ICs at the 2023 International Test Conference (ITC) on Oct. 8-13 at the Disneyland Convention Center in Anaheim, California.
  • International Test Conference is the world’s premier conference dedicated to the electronic test of devices, boards and systems-covering the complete cycle from design verification, test, diagnosis, failure analysis and back to process and design improvement.
  • Advantest's product showcase in booth #217 will highlight the company’s broad portfolio, including ATE, device interface, System Level Test (SLT) and analytics solutions that add customer value to the evolving semiconductor value chain.
  • The seamless portability of the structural test patterns developed for ATE platform ( Advantest V93000 ) on to ATS 7038 will be featured as well.

Synopsys and TSMC Streamline Multi-Die System Complexity with Unified Exploration-to-Signoff Platform and Proven UCIe IP on TSMC N3E Process

Retrieved on: 
Wednesday, September 27, 2023
PHY, HBM3, IP, UCIe, SNPS, Compiler, TSMC, Architecture, Silicon, Extrusion, Semiconductor, Printed circuit board, Ansys, Synopsys

SUNNYVALE, Calif., Sept. 27, 2023 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) today announced it is extending its collaboration with TSMC to advance multi-die system designs with a comprehensive solution supporting the latest 3Dblox 2.0 standard and TSMC's 3DFabric™ technologies. The Synopsys Multi-Die System solution includes 3DIC Compiler, a unified exploration-to-signoff platform that delivers the highest levels of design efficiency for capacity and performance. In addition, Synopsys has achieved first-pass silicon success of its Universal Chiplet Interconnect Express (UCIe) IP on TSMC's leading N3E process for seamless die-to-die connectivity.

Key Points: 
  • Synopsys UCIe PHY IP, which achieved first-pass silicon success on TSMC N3E process, provides low-latency, low-power, and high-bandwidth die-to-die connectivity.
  • The combination of UCIe PHY IP and 3DIC Compiler optimizes multi-die system design for higher quality-of-results with minimal integration risk.
  • The Synopsys Multi-Die System solution includes 3DIC Compiler, a unified exploration-to-signoff platform that delivers the highest levels of design efficiency for capacity and performance.
  • Synopsys UCIe PHY IP on the TSMC N3E process and 3DIC Compiler are available now.

Cadence Advances Hyperscale SoC Design with Expanded IP Portfolio for TSMC N3E Process Featuring Next-Generation 224G-LR SerDes IP

Retrieved on: 
Wednesday, September 20, 2023
Electronic Design Automation, Data Management, Semiconductor, Technology, 5G, Artificial Intelligence, Hardware, LLM, Cadence Design Systems, IP Group, PHY, CDNS, SerDes, LR, PCI Express, IP, Chiplet, SOC, UCIe, DDR5, PCI, Machine learning, Media, Hyperscale computing, TSMC, Artificial intelligence, Silicon, VSR, PPA, Cassette tape, Cable television, Cadence

Other Cadence Design IP on the advanced TSMC N3E process has demonstrated silicon success or taped out, providing mutual customers with a wide range of high-speed interface and memory IP for their most advanced designs.

Key Points: 
  • Other Cadence Design IP on the advanced TSMC N3E process has demonstrated silicon success or taped out, providing mutual customers with a wide range of high-speed interface and memory IP for their most advanced designs.
  • Addressing this surging demand, the new 224G-LR SerDes PHY IP and other leading Cadence interface IP on the TSMC N3E process usher in a new era of innovation and high-speed connectivity.
  • Our close collaboration with TSMC enables us to deliver high-quality IP designed to achieve first-pass silicon success and faster time to market.”
    The comprehensive Cadence IP portfolio on the TSMC N3E process supports the Cadence Intelligent System Design™ strategy by enabling advanced-node SoC design excellence.
  • For more information about Cadence’s next-generation 224G SerDes PHY IP and the comprehensive Cadence N3E Design IP portfolio, please visit www.cadence.com/go/N3EDIPPR .