RISC | Jotup

Global and China Automotive RISC-V Chip Industry Research Report 2024: Customized Chips May Become the Future Trend, and RISC-V will Challenge ARM

Retrieved on:

Friday, March 15, 2024

ISA, Research, Certification, IO, SOC, Memory, Veyron, Qualcomm, Computing, Threshold, Electronics, RISC, Internet, IATF, ARM, IDE, Software, Architecture, IP, SiFive, Ecosystem, X86, NXP, Patent, Family, CPU, Economics, UCIe, ICT, Video game

DUBLIN, March 14, 2024 /PRNewswire/ -- The "Automotive RISC-V Chip Industry Research Report, 2024" report has been added to ResearchAndMarkets.com's offering.

Key Points:

DUBLIN, March 14, 2024 /PRNewswire/ -- The "Automotive RISC-V Chip Industry Research Report, 2024" report has been added to ResearchAndMarkets.com's offering.
In contrast, ARM and X86 are not only complicated in instruction set development, but also difficult to obtain authorization to modify instruction sets.
In terms of customization, it enables designers to create thousands of potential customized processors, thus speeding up the time to market.
In the past, automotive chips were mainly based on ARM or private architectures of some European chip companies.

RISC-V Processors Addressing Edge AI Devices to Reach 129 Million Shipments by 2030

Retrieved on:

Wednesday, February 14, 2024

LONDON, Feb. 14, 2024 /PRNewswire/ -- Reduced Instruction Set Computing (RISC)-V processor architectures are starting to address edge Artificial Intelligence (AI) workloads, and this trend is set to continue throughout the decade. According to a new report from global technology intelligence firm ABI Research, while RISC-V's penetration into AI workloads is only just beginning, growth will be steady throughout the rest of the decade, pushing RISC-V chip shipments in edge AI (excluding TinyML) to 129 million by 2030.

Key Points:

According to a new report from global technology intelligence firm ABI Research, while RISC-V's penetration into AI workloads is only just beginning, growth will be steady throughout the rest of the decade, pushing RISC-V chip shipments in edge AI (excluding TinyML) to 129 million by 2030.
Leading startups, like Axelera AI and Tenstorrent , show RISC-V's potential to address more demanding AI inferencing workloads, like computer vision in automotive and security applications.
Legacy players, from Qualcomm to Microchip , also want to develop processors using the Instruction Set Architecture (ISA).
A key driver of shipment numbers is edge AI gateways, the bulk of which comprises systems connecting and performing inference on sensors in the home.

RISC-V Processors Addressing Edge AI Devices to Reach 129 Million Shipments by 2030

Retrieved on:

Wednesday, February 14, 2024

LONDON, Feb. 14, 2024 /PRNewswire/ -- Reduced Instruction Set Computing (RISC)-V processor architectures are starting to address edge Artificial Intelligence (AI) workloads, and this trend is set to continue throughout the decade. According to a new report from global technology intelligence firm ABI Research, while RISC-V's penetration into AI workloads is only just beginning, growth will be steady throughout the rest of the decade, pushing RISC-V chip shipments in edge AI (excluding TinyML) to 129 million by 2030.

Key Points:

According to a new report from global technology intelligence firm ABI Research, while RISC-V's penetration into AI workloads is only just beginning, growth will be steady throughout the rest of the decade, pushing RISC-V chip shipments in edge AI (excluding TinyML) to 129 million by 2030.
Leading startups, like Axelera AI and Tenstorrent , show RISC-V's potential to address more demanding AI inferencing workloads, like computer vision in automotive and security applications.
Legacy players, from Qualcomm to Microchip , also want to develop processors using the Instruction Set Architecture (ISA).
A key driver of shipment numbers is edge AI gateways, the bulk of which comprises systems connecting and performing inference on sensors in the home.

BellSoft releases Liberica JDK 21 for RISC-V with support

Retrieved on:

Tuesday, January 30, 2024

SAN, Java, RISC, JDK, Linux, Language, OpenJDK, ARM, VMS, ISA, Intel, Internet of things, LTS

We now have tailored Liberica JDK builds for RISC-V , so you can port your applications without any issue.

Key Points:

We now have tailored Liberica JDK builds for RISC-V , so you can port your applications without any issue.
Liberica JDK builds for Linux on RISC-V are available starting from JDK 21 LTS.
BellSoft is committed to supporting version 21 until 2032.
Liberica JDK Standard is a base Liberica JDK flavor with three VMs and all garbage collectors, designed specifically for running Java on RISC-V in a highly performant and cost-efficient way.

Five Leading Semiconductor Industry Players Incorporate New Company, Quintauris, to Drive RISC-V Ecosystem Forward

Retrieved on:

Friday, December 22, 2023

Semiconductor, IOT (Internet of Things), Hardware, Technology, Software, Ecosystem, Infineon Technologies, Nordic Semiconductor, RISC, University, Internet of things, Element, Consumer electronics

Semiconductor industry players Robert Bosch GmbH, Infineon Technologies AG, Nordic Semiconductor ASA, NXP® Semiconductors, and Qualcomm Technologies, Inc., have formally established Quintauris GmbH.

Key Points:

Semiconductor industry players Robert Bosch GmbH, Infineon Technologies AG, Nordic Semiconductor ASA, NXP® Semiconductors, and Qualcomm Technologies, Inc., have formally established Quintauris GmbH.
Headquartered in Munich, Germany, the company aims to advance the adoption of RISC-V globally by enabling next-generation hardware development.
The initial application focus will be automotive, but with an eventual expansion to include mobile and IoT.
We are fortunate to have the backing of some of the most established players in the semiconductor industry, which shows our ambition for Quintauris to be a long-term, sustainable offer.

Captive Industry Specialist Amanda Wescott Joins NFP's Risk and Insurance Strategy Collective

Retrieved on:

Tuesday, August 29, 2023

Growth, RISC, Risk, Risk management, NFP, Wescott, Amanda, Marsh, Mackenzie, Insurance

NEW YORK, Aug. 29, 2023 /PRNewswire/ -- NFP, a leading property and casualty broker, benefits consultant, wealth manager and retirement plan advisor, today announced that Amanda Wescott has joined the company's Risk and Insurance Strategy Collective (RISC) as vice president, director of US captive management operations. RISC is a specialty practice that provides a comprehensive range of captive management solutions. Wescott's hire reflects NFP's commitment to the captive industry and focus on building specialist teams that help clients solve their complex risks.

Key Points:

Wescott's hire reflects NFP's commitment to the captive industry and focus on building specialist teams that help clients solve their complex risks.
Wescott will assist with the growth and advancement of risk management solutions for new and existing clients, while leading a team of captive insurance professionals.
Wescott joins RISC with more than 15 years of captive and risk management experience.
Wescott is an active member of many trade associations and will continue to serve on various committees within the captive industry.

SAFERTOS From WITTENSTEIN high integrity systems Supports The AURIX™ TriCore™ from Infineon To Form A Compelling Automotive Solution

Retrieved on:

Wednesday, July 12, 2023

Real, MCU, ISO, DSP, Automotive industry, Risk, RISC, WHIS, DAP, Safety, Online shopping, BRISTOL, Infineon Technologies

BRISTOL, England, July 12, 2023 /PRNewswire-PRWeb/ -- SAFERTOS is optimized for the Infineon AURIX™ TriCore™ and is used across a wide range of applications within the automotive industry. Recognizing the growing need for secure and reliable embedded solutions, WITTENSTEIN high integrity systems (WHIS) offer an automotive RTOS package that delivers responsive functionality in a networked environment and is available pre-certified to ISO 26262 by TÜV SÜD. The AURIX™ TriCore™ unites the elements of a RISC processor core, a microcontroller and a DSP in one single MCU, making SAFERTOS an excellent fit with the AURIX™ TriCore™ for safety critical applications.

Key Points:

SAFERTOS, the safety-certified real time operating system from WITTENSTEIN high integrity systems, supports the AURIX™ TriCore™ from Infineon.
BRISTOL, England, July 12, 2023 /PRNewswire-PRWeb/ -- SAFERTOS is optimized for the Infineon AURIX™ TriCore™ and is used across a wide range of applications within the automotive industry.
SAFERTOS evaluation packages offer engineers access to full SAFERTOS source code, an 'out of the box' SAFERTOS demonstration application, and a comprehensive user manual.
"The safety qualifications of SAFERTOS make it an excellent solution for automotive developers working with the AURIX™ TriCore™" said Andrew Longhurst, Managing Director for WITTENSTEIN high integrity systems.

MIPS Leverages Siemens' Veloce proFPGA platform to Implement and Make Available Capabilities of its New High-Performance eVocore P8700 RISC-V Multiprocessor

Retrieved on:

Tuesday, May 30, 2023

Ethernet, Siemens Digital Industries Software, PCI Express, SOC, IP, CPU, SAN, MIPS, OOO, Logic, Architecture, RISC, HW, ADAS, Silicon, FPGA, Mobile phone, Video game, Veloce

SAN JOSE, Calif., May 30, 2023 /PRNewswire/ -- MIPS, a leading developer of highly scalable RISC processor IP, has collaborated with Siemens Digital Industries Software, a global electronic design automation leader, to speed time-to-market and accelerate software development for customers of the new MIPS eVocore P8700 RISC-V multiprocessor.

Key Points:

Under the collaboration, MIPS will use Siemens' Veloce™ proFPGA platform to demonstrate MIPS' high-performance intellectual property (IP) cores, including MIPS' eVocore P8700 , which recently took top honors at Embedded World.
The P8700, one of the industry's highest performance, most scalable RISC-V multiprocessor IP, has already been adopted for applications including autonomous driving and advanced driver assistance systems (ADAS).
MIPS CPUs on Siemens' Veloce proFPGA platform can enable customers to validate their end systems before silicon.
Siemens' Veloce proFPGA platform can dramatically lower the adoption barrier of the FPGA desktop prototype solution.

University of Chicago's Market Shaping Accelerator Launches $2 Million Innovation Challenge

Retrieved on:

Thursday, May 25, 2023

CHICAGO, May 25, 2023 /PRNewswire/ -- The University of Chicago's Market Shaping Accelerator (MSA) today announced its $2 million Innovation Challenge. Launched earlier this month, the MSA aims to accelerate efforts to address major global challenges by leveraging the power of incentives, competition, and private sector innovation. In its first year, the MSA and Innovation Challenge are focused on incentivizing groundbreaking solutions for climate change, biosecurity, and pandemic preparedness.

Key Points:

Newly launched Accelerator to crowdsource ideas and support innovations to address global threats related to climate change, biosecurity, and pandemic preparedness
CHICAGO, May 25, 2023 /PRNewswire/ -- The University of Chicago's Market Shaping Accelerator (MSA) today announced its $2 million Innovation Challenge.
In its first year, the MSA and Innovation Challenge are focused on incentivizing groundbreaking solutions for climate change, biosecurity, and pandemic preparedness.
The MSA will then work with policymakers, domain experts and funders to develop market shaping instruments tailored to selected problems.
Market shaping uses economic tools to solve market failures where commercial incentives for innovation trail behind societal needs.

SGNL Announces caep.dev, The First Free Continuous Access Evaluation Protocol / Profile (CAEP) Transmitter

Retrieved on:

Tuesday, April 11, 2023

Momentum, Shared, OpenID, PALO, Microsoft, Identity, IDSA, Research, Blog, CAEP, Organization, Cisco, Zero trust security model, SSF, SGNL, RISC, Online shopping

PALO ALTO, Calif., April 11, 2023 /PRNewswire/ -- SGNL, the company modernizing enterprise authorization, today announced the launch of a free, non-commercial Continuous Access Evaluation Protocol / Profile (CAEP) Transmitter. This new offering further demonstrates SGNL's commitment to and leadership in standards development and adoption.

Key Points:

PALO ALTO, Calif., April 11, 2023 /PRNewswire/ -- SGNL, the company modernizing enterprise authorization, today announced the launch of a free, non-commercial Continuous Access Evaluation Protocol / Profile (CAEP) Transmitter.
"caep.dev not only provides a ready Transmitter, it also shows how easy it is to build and adopt CAEP Receivers."
SGNL's caep.dev offering includes the following features:
The Continuous Access Evaluation Protocol was first conceived in a blog post by Google.
Momentum has been building around CAEP: Microsoft announced their Continuous Access Evaluation feature and Cisco announced a website dedicated to Shared Signals - sharedsignals.guide , and associated open source components.