Chiplet

ASE’s VIPack™ Enables Innovational AI Devices Through Advanced Interconnect Technology for Chiplets

Retrieved on: 
Wednesday, March 20, 2024
Semiconductor, Engineering, Technology, Manufacturing, Artificial Intelligence, Hardware, IO, AP, SOC, Integration, Artificial intelligence, TAIEX, IDE, AI, Senior, Marketing, IP, Creativity, Chiplet, Corporation, Printed circuit board

This interconnect extension advances roadmap capabilities from a chip-on-wafer interconnect pitch of 40um to 20um through advanced microbump technology.

Key Points: 
  • This interconnect extension advances roadmap capabilities from a chip-on-wafer interconnect pitch of 40um to 20um through advanced microbump technology.
  • As the chiplet design approach accelerates, ASE’s advanced interconnect technology allows designers to consider innovative, high density chiplet integration options where there might normally be chip IO density limitations for true 3D layered IP block considerations.
  • ASE’s microbump technology allows for a reduction in pitch from 40um down to 20um using a new metallurgical stack.
  • Fine pitch interconnect capabilities enable a 3D integration capability as well as a higher density for high IO memory considerations.

Cadence Collaborates with Arm to Jumpstart the Automotive Chiplet Ecosystem

Retrieved on: 
Wednesday, March 13, 2024
Automotive Manufacturing, Automotive, Technology, Manufacturing, Semiconductor, Vehicle Technology, Software, Artificial Intelligence, Engineering, Hardware, Electronic Design Automation, SOC, DSP, Prevalence, Chiplet, Electronics, ADAS, Blog, CDNS, 3D, AI, SDV, Cadence Design Systems, Architecture, Scalability, IP, NPU, Ecosystem, Workload, Machine learning, SDK, Silicon

The automotive reference design, initially for advanced driver assistance system (ADAS) applications, specifies a scalable chiplet architecture and interface interoperability to foster industry-wide collaboration, enable heterogeneous integration and expand system innovation.

Key Points: 
  • The automotive reference design, initially for advanced driver assistance system (ADAS) applications, specifies a scalable chiplet architecture and interface interoperability to foster industry-wide collaboration, enable heterogeneous integration and expand system innovation.
  • The solution is architected and built using the latest generation of Arm® Automotive Enhanced technologies and Cadence® IP.
  • Coupled with the need to quickly customize 3D-IC systems for a plethora of automotive applications, chiplets are an increasingly attractive solution.
  • The new solution architecture and reference design provide a standard for chiplet interface interoperability, addressing a critical industry need.

Silicon Box cutting-edge, advanced panel-level packaging foundry announces $3.6B investment for expansion into Italy

Retrieved on: 
Tuesday, March 12, 2024
Dai, Automation, EV, Socs, Conference, Environment, Original equipment manufacturer, EVS, Intelligence, Business, Education, HPC, Sips, Artificial intelligence, Carbon footprint, Carbon, LLM, Chiplet, Investment, Semiconductor, European, Ecosystem, European Commission, Sustainability, IDMS, Government, ISSCC, Renewable energy

ROME, March 12, 2024 /PRNewswire/ -- Silicon Box cutting-edge, advanced panel-level packaging foundry announced its intention to collaborate with the Italian government to invest up to $3.6B (€3.2B) in Northern Italy, as the site of a new, state-of-the-art semiconductor assembly and test facility. This facility will help meet critical demand for advanced packaging capacity to enable next generation technologies that Silicon Box anticipates by 2028. The multi-year investment will replicate Silicon Box's flagship foundry in Singapore which has proven capability and capacity for the world's most advanced semiconductor packaging solutions, then expand further into 3D integration and testing. When completed, the new facility will support approximately 1,600 Silicon Box employees in Italy. The construction of the facility is also expected to create several thousand more jobs, including eventual hiring by suppliers. Design and planning for the facility will begin immediately, with construction to commence pending European Commission approval of planned financial support by the Italian State.

Key Points: 
  • This facility will help meet critical demand for advanced packaging capacity to enable next generation technologies that Silicon Box anticipates by 2028.
  • Through the investment, Silicon Box has plans for greater innovation and expansion in Europe, and globally.
  • "We are excited to bring Italy to the forefront of chiplet deployment and the semiconductor industry, through this investment into the world's most advanced packaging solution.
  • Notably, Silicon Box facilities specialize in advanced chiplet integration capabilities ("advanced packaging"), on a large manufacturing format for scale.

Silicon Box cutting-edge, advanced panel-level packaging foundry announces $3.6B investment for expansion into Italy

Retrieved on: 
Tuesday, March 12, 2024
Dai, Automation, EV, Socs, Conference, Environment, Original equipment manufacturer, EVS, Intelligence, Business, Education, HPC, Sips, Artificial intelligence, Carbon footprint, Carbon, LLM, Chiplet, Investment, Semiconductor, European, Ecosystem, European Commission, Sustainability, IDMS, Government, ISSCC, Renewable energy

ROME, March 12, 2024 /PRNewswire/ -- Silicon Box cutting-edge, advanced panel-level packaging foundry announced its intention to collaborate with the Italian government to invest up to $3.6B (€3.2B) in Northern Italy, as the site of a new, state-of-the-art semiconductor assembly and test facility. This facility will help meet critical demand for advanced packaging capacity to enable next generation technologies that Silicon Box anticipates by 2028. The multi-year investment will replicate Silicon Box's flagship foundry in Singapore which has proven capability and capacity for the world's most advanced semiconductor packaging solutions, then expand further into 3D integration and testing. When completed, the new facility will support approximately 1,600 Silicon Box employees in Italy. The construction of the facility is also expected to create several thousand more jobs, including eventual hiring by suppliers. Design and planning for the facility will begin immediately, with construction to commence pending European Commission approval of planned financial support by the Italian State.

Key Points: 
  • This facility will help meet critical demand for advanced packaging capacity to enable next generation technologies that Silicon Box anticipates by 2028.
  • Through the investment, Silicon Box has plans for greater innovation and expansion in Europe, and globally.
  • "We are excited to bring Italy to the forefront of chiplet deployment and the semiconductor industry, through this investment into the world's most advanced packaging solution.
  • Notably, Silicon Box facilities specialize in advanced chiplet integration capabilities ("advanced packaging"), on a large manufacturing format for scale.

Ceva Joins Arm Total Design to Accelerate Development of End-to-End 5G SoCs for Infrastructure and NTN Satellites

Retrieved on: 
Wednesday, February 28, 2024
CEVA, Chiplet, Socs, Silicon, PHY, Internet of things, MWC, CPU, L1, Risk, COTS, High-pass filter, Ecosystem, NTN, IP, SOC, DSPS, CSS, FPGA, Video game

BARCELONA, Spain, Feb. 28, 2024 /PRNewswire/ -- MWC Barcelona 2024 - Ceva, Inc. (NASDAQ: CEVA), the leading licensor of silicon and software IP that enables Smart Edge devices to connect, sense and infer data more reliably and efficiently, announced today that it has joined Arm Total Design, with the aim of accelerating the development of end-to-end 5G custom SoCs based on Arm® Neoverse™ Compute Subsystems (CSS) and the Ceva PentaG-RAN 5G platform, for wireless infrastructure including 5G base stations, Open RAN equipment and 5G non-terrestrial-networks (NTN) satellites.

Key Points: 
  • Neoverse CSS are optimized, integrated and verified platforms which enable custom silicon designs at lower cost and a faster time-to-market.
  • "Arm Total Design enables a new era of innovation and collaboration on Neoverse CSS, empowering the ecosystem built around Arm to design custom silicon optimized for any application," said Eddie Ramirez, vice president of go-to-market, Infrastructure Line of Business, Arm.
  • "The Neoverse compute subsystem incorporating our Ceva PentaG-RAN 5G platform delivers a compelling solution to the market, lowering the entry barriers for companies looking to address new 5G markets like Open RAN and 5G NTN satellite networks."
  • The Ceva PentaG-RAN platform is RF front-end agnostic, ensuring it can be utilized for the development of 5G systems targeting mmWave and sub-6-GHz networks.

Tenstorrent RISC-V and Chiplet Technology Selected to Build the Future of AI in Japan

Retrieved on: 
Tuesday, February 27, 2024
Workload, Rapidus, Chiplet, Silicon, Intelligence, LSTC, IPad, CPU, MOC, Organization, AMD, Apple, Partnership, Video game

In addition to the IP licensing portion of this deal, Tenstorrent will work with LSTC as a collaborative innovation partner to co-design the chip that will redefine AI performance in Japan.

Key Points: 
  • In addition to the IP licensing portion of this deal, Tenstorrent will work with LSTC as a collaborative innovation partner to co-design the chip that will redefine AI performance in Japan.
  • Long known to offer the highest performing RISC-V CPU technology in the market, Tenstorrent will leverage its Ascalon RISC-V CPU core technology to co-develop a RISC-V CPU chiplet for LSTC's new edge AI accelerator.
  • "The edge AI accelerator will incorporate LSTC's AI chiplet along with Tenstorrent's RISC-V and peripheral chiplet technology.
  • "As a next-generation semiconductor design technology, we will promote the development of edge AI accelerators dedicated to edge inference processing applications, including generative AI, through international collaboration.

$148 Billion Chiplet Market by Processor, Packaging Technology - Global Forecast to 2028

Retrieved on: 
Monday, February 19, 2024
HPC, AMD, Nvidia, USD, Chiplet, Artificial intelligence, Research, Investment, APU, WLCSP, IBM, Internet of things, CPU, Growth, Electronics, Big data, Intel, GPU, Field-programmable gate array, Ecosystem, Intellectual property, SIP, Gate array, Central processing unit, Apple Inc., Research report, College of Engineering (KNUST), FPGA, Graphics processing unit, Medical device

This research report categorizes the chiplet market on the basis of processor, packaging technology, end-use application, and region.

Key Points: 
  • This research report categorizes the chiplet market on the basis of processor, packaging technology, end-use application, and region.
  • The report describes the major drivers, restraints, challenges, and opportunities pertaining to the chiplet market and forecasts the same till 2028.
  • Asia Pacific is expected to hold a major market share for chiplet market during the forecast period.
  • Market Diversification: Exhaustive information about new products & services, untapped geographies, recent developments, and investments in the chiplet market

Adeia Demonstrates Hybrid Bonding Technology During Chiplet Summit 2024

Retrieved on: 
Tuesday, February 6, 2024
Chiplet, ADEA, Santa Clara Convention Center, Engineering, Conference, PST, Video game

SANTA CLARA, Calif., Feb. 06, 2024 (GLOBE NEWSWIRE) -- Adeia Inc. (Nasdaq: ADEA), the company whose patented innovations enhance billions of devices, today announced that it is showcasing its hybrid bonding technology at the Chiplet Summit on February 6 through 8, 2024, at the Santa Clara Convention Center.

Key Points: 
  • SANTA CLARA, Calif., Feb. 06, 2024 (GLOBE NEWSWIRE) -- Adeia Inc. (Nasdaq: ADEA), the company whose patented innovations enhance billions of devices, today announced that it is showcasing its hybrid bonding technology at the Chiplet Summit on February 6 through 8, 2024, at the Santa Clara Convention Center.
  • With an extensive and growing portfolio of intellectual property covering hybrid bonding, advanced process nodes and advanced packaging technologies, Adeia licenses and partners with leading semiconductor companies worldwide.
  • Adeia’s hybrid bonding technology is increasingly being adopted in sensors, memory chips and logic devices, enhancing performance and functionality while reducing size and cost,” added Laura Mirkarimi, senior vice president, engineering at Adeia.
  • To find demonstrations and presentations by Adeia during the Chiplet Summit, visit:
    Adeia Booth #317 – The Adeia team will showcase the latest innovations in hybrid bonding technology.

Credo Launches 112G PAM4 SerDes IP for TSMC N3 Process Technology

Retrieved on: 
Thursday, February 1, 2024
Technology, Internet, Hardware, Data Management, Multimedia, Copper, Family, AI, Application-specific integrated circuit, DSP, N3, N4, Machine learning, Credo, Documentation, Business development, VSR, Chiplet, IP, PAM4, Silicon, Architecture, Original equipment manufacturer, Network switch, 3D printing

Credo Technology Group Holding Ltd (NASDAQ: CRDO) today introduced its newest 112G PAM4 SerDes Intellectual Property (IP) family on TSMC’s industry leading N3 and N7/N6 process technologies.

Key Points: 
  • Credo Technology Group Holding Ltd (NASDAQ: CRDO) today introduced its newest 112G PAM4 SerDes Intellectual Property (IP) family on TSMC’s industry leading N3 and N7/N6 process technologies.
  • These two new SerDes IPs complement Credo’s available IP in TSMC’s N5 process technology, which also includes the enhanced N4 version of the 5nm node.
  • Credo then ported the 12nm, 112G SerDes to more advanced process technology nodes (N7/N6, N5/N4, and N3) – allowing customers to integrate the silicon proven technology into monolithic ASICs and chiplets.
  • These new 112G PAM4 SerDes IP were designed to meet the growing data needs of high-speed, data-intensive applications.

Cadence Significantly Advances ECAD/MCAD Convergence for Electronic Systems with New Celsius Studio AI Thermal Platform

Retrieved on: 
Wednesday, January 31, 2024
Electronic Design Automation, Engineering, Semiconductor, Technology, Manufacturing, Software, Hardware, Multimedia, MMIC, Electronics, Workflow, RF, Optimality, Samsung Electronics, AWR, IC, Gallium nitride, BAE, CDNS, Simulation, Acquisition, Chiplet, Polychlorinated biphenyl, Algorithm, Studio, Cadence Design Systems, 3D-IC, PCB, Video game

Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced Cadence® Celsius™ Studio, the industry’s first complete AI thermal design and analysis solution for electronic systems.

Key Points: 
  • Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced Cadence® Celsius™ Studio, the industry’s first complete AI thermal design and analysis solution for electronic systems.
  • Celsius Studio addresses thermal analysis and thermal stress for 2.5D and 3D-ICs and IC packaging, in addition to electronics cooling for PCBs and complete electronic assemblies.
  • View the full release here: https://www.businesswire.com/news/home/20240131987413/en/
    The industry’s first complete AI thermal design and analysis solution for electronic systems, Cadence® Celsius™ Studio addresses thermal analysis and thermal stress for 2.5D and 3D-ICs and IC packaging, in addition to electronics cooling for PCBs and complete electronic assemblies.
  • Customers interested in gaining early access to Celsius Studio should contact their Cadence account representative.