Integrated circuit design

GBT Commenced Design Productivity Software Solutions Development

Retrieved on: 
Monday, November 2, 2020
Integrated circuits, Electrical engineering, Digital electronics, Electronic engineering, Electronic design, Integrated circuit design, Design rule checking, DEC Alpha, Physical design

SAN DIEGO, Nov. 02, 2020 (GLOBE NEWSWIRE) -- GBT Technologies Inc. (OTC PINK: GTCH) ("GBT, or the Company) announced that GBT together with Alpha EDA (Alpha), its joint venture partner, have developed IC design productivity enhancement algorithms and methods.

Key Points: 
  • SAN DIEGO, Nov. 02, 2020 (GLOBE NEWSWIRE) -- GBT Technologies Inc. (OTC PINK: GTCH) ("GBT, or the Company) announced that GBT together with Alpha EDA (Alpha), its joint venture partner, have developed IC design productivity enhancement algorithms and methods.
  • The geometrical/physical design rules of the tiny transistors are becoming a bottleneck when it comes to achieving reasonable chips design time.
  • In addition, Alpha's productivity solutions address electrical rules violations in order to maintain chip's power efficiency, high reliability, and high performance operation.
  • Economy condition enforces IC design houses to move to more cost-effective design processes in order to stay in business.

Cadence Custom/AMS Flow Certified for the Samsung Foundry 3nm Advanced Process Technology for Early Design Starts

Retrieved on: 
Wednesday, October 28, 2020
Software, Technology, Mobile, Wireless, Hardware, Companies, Industries, Home appliances, Cadence Design Systems, 3 nm process, Samsung Electronics, Integrated circuit design

Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that its custom and analog/mixed-signal (AMS) IC design flow has achieved certification for Samsung Foundrys 3nm GAA process technology for early design starts.

Key Points: 
  • Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that its custom and analog/mixed-signal (AMS) IC design flow has achieved certification for Samsung Foundrys 3nm GAA process technology for early design starts.
  • The automated Cadence custom and AMS full flow supports the companys Intelligent System Design strategy, enabling SoC design excellence.
  • For more information on the Cadence custom and AMS flow that supports the Samsung 3nm process technology, visit www.cadence.com/go/CadenceSamsungAMS3nm .
  • When designing for the 3nm GAA process, the Cadence Virtuoso layout flow provides a high level of automation and integration, enabling faster design closure with reduced numbers of iterations.

Synopsys to Enable New Levels of Insight into SoC Designs and Systems with Industry's First Silicon Lifecycle Management Platform

Retrieved on: 
Monday, October 12, 2020
Electronic engineering, Synopsys, Integrated circuits, Electronic design, Integrated circuit design, Life cycle, Computer engineering, Electrical engineering

The SLM platform, which is tightly coupled with Synopsys' market-leading Fusion Design Platform, will provide visibility into critical performance, reliability and security issues for the entirety of a chip's lifespan.

Key Points: 
  • The SLM platform, which is tightly coupled with Synopsys' market-leading Fusion Design Platform, will provide visibility into critical performance, reliability and security issues for the entirety of a chip's lifespan.
  • It will enable new levels of insights for both SoC teams and their customers and provide the ability to optimize operational activities at each stage of the device and system lifecycles.
  • "Building on our core expertise in IC design, our SLM platform provides a game-changing set of optimization capabilities that extend throughout the entire lifecycle of IC design, production and deployment."
  • To hear more about the Synopsys SLM platform, attend the Silicon Lifecycle Management track at the Digital Design Technology Symposium to be held virtually on Wednesday, Oct. 14.

Synopsys Names Shankar Krishnamoorthy General Manager of the Digital Design Group

Retrieved on: 
Monday, October 12, 2020
Electronic engineering, Digital electronics, Design, Synopsys, Integrated circuits, Electronic design automation, High-level synthesis, Physical design, Integrated circuit design

MOUNTAIN VIEW, Calif., Oct. 12, 2020 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS ) today announced that Shankar Krishnamoorthy has been promoted to GM of the Digital Design Group.

Key Points: 
  • MOUNTAIN VIEW, Calif., Oct. 12, 2020 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS ) today announced that Shankar Krishnamoorthy has been promoted to GM of the Digital Design Group.
  • Krishnamoorthy, who rejoined Synopsys in 2017, is an electronic design automation veteran with 25 years of experience bringing to market high-value, market-leading physical design and logic synthesis solutions.
  • Most recently, he was senior vice president of the Digital Implementation group, where he led the development and delivery of Synopsys' game-changing innovations including Fusion Compiler, RTL Architect, 3DIC Compiler and Synopsys TestMAX solutions.
  • "The Synopsys Digital Design Group has been at the forefront of leading innovation in the EDA industry to enable our customers to achieve their power, performance and area ambitions in shrinking market windows," said Shankar Krishnamoorthy.

Edaptive Computing and OneSpin Launch Formal Verification Certification Program to Promote Best Practices for Meeting IC Integrity Standards

Retrieved on: 
Monday, October 5, 2020
Technology, General Automotive, Engineering, Automotive Manufacturing, Aerospace, Manufacturing, Automotive, Training, Telecommunications, Software, Education, Hardware, Electronic design automation, Semiconductor, Theoretical computer science, Electronic engineering, Digital electronics, Design, Electronic design, Verification, Formal verification, Formal methods, Integrated circuit design, Intelligent verification, Signoff, OneSpin Solutions, Edaptive Computing, Inc.

The program provides comprehensive training of formal methods theory, techniques and their application to real-world hardware designs using the OneSpin Design Verification 360 Solutions .

Key Points: 
  • The program provides comprehensive training of formal methods theory, techniques and their application to real-world hardware designs using the OneSpin Design Verification 360 Solutions .
  • Formal is a critical part of companies verification methodology and every company will benefit from having the expertise to match.
  • Working with OneSpin will allow us to transfer our formal verification knowledge and expertise to organizations needing to verify IC design integrity.
  • OneSpin Solutions is a leading provider of certified IC integrity verification solutions for building functionally correct, safe, secure and trusted integrated circuits.

Synopsys Introduces the Industry's First Unified Electronic and Photonic Design Platform

Retrieved on: 
Wednesday, September 9, 2020
Electromagnetism, Optics, Electrical engineering, Electronic engineering, Integrated circuits, Photonic integrated circuit, Synopsys, Photonics, Electronic design automation, Integrated circuit design, Photonic crystal

OptoCompiler combines specific capabilities for photonic design with industry-proven electronic design methods in a unique, unified platform to make photonic IC design accessible, fast, and flexible

Key Points: 
  • OptoCompiler combines specific capabilities for photonic design with industry-proven electronic design methods in a unique, unified platform to make photonic IC design accessible, fast, and flexible
    Synopsys, Inc. (Nasdaq:SNPS) today introduced its OptoCompiler solution for photonic integrated circuit (PIC) design, layout implementation and verification.
  • OptoCompiler is the industry's first unified electronic and photonic design platform, combining mature and dedicated photonic technology with Synopsys' industry-proven electronic design tools and methods to enable engineers to produce and verify complex PIC designs quickly and accurately.
  • By providing schematic-driven layout and advanced photonic layout synthesis in a single platform, OptoCompiler bridges the gap between photonic experts and IC designers to make photonic design accessible, fast, and flexible.
  • "With OptoCompiler, we aim to make photonic design as productive as digital," said Tom Walker, group director of Synopsys' Photonic Solutions.

Keysight Technologies Accelerates 5G Design, Simulation and Verification Workflows with PathWave Design 2021 Software Suite

Retrieved on: 
Monday, July 20, 2020
Mobile, Wireless, Technology, Semiconductor, Automotive Manufacturing, Aerospace, Software, Manufacturing, Networks, Hardware, Electronic design automation, Digital electronics, Electronic engineering, Electronic design automation, Integrated circuits, PathWave Design, Electronic system-level design and verification, Advanced Design System, RFIC, 5G, Integrated circuit design, Goldengate, Logic simulation

Current design methodologies for 4G and earlier standards use approximate figures of merit to get designs to market quickly, said Tom Lillig, general manager of PathWave Software Solutions at Keysight Technologies.

Key Points: 
  • Current design methodologies for 4G and earlier standards use approximate figures of merit to get designs to market quickly, said Tom Lillig, general manager of PathWave Software Solutions at Keysight Technologies.
  • PathWave 5G addresses high frequency and complexity with new capabilities across all design phases including simulation to validation, as well as test and manufacturing.
  • Keysights PathWave Design 2021 software suite enables:
    Power amplifier designers using RF Gallium Nitride (GaN) superior power, size and efficiency advantages to model trapping and thermal effects.
  • Keysights PathWave Design software suite includes: PathWave Advanced Design System (ADS), PathWave RFIC Design (GoldenGate), PathWave System Design (SystemVue), PathWave EM Design (EMPro) and PathWave Device Modeling (IC-CAP ), which deliver the key capabilities needed to address 5G challenges, including radio frequency/microwave (RF/MW) simulation and verification; electronic system-level (ESL) simulation; and device modeling to improve design speed, accuracy and robustness.

Presto Engineering Moves to New Facility in Caen for Enhanced Engineering and Production Capabilities

Retrieved on: 
Monday, July 13, 2020
Semiconductor, Hardware, Manufacturing, Technology, Engineering, Articles, Business, Economy, Ambient intelligence, Digital technology, Internet of things, Technology assessment, Presto, Integrated circuit design, Outsourcing

The facility will provide IC test, qualification, and test production services primarily for communications, automotive, IoT, and industrial applications.

Key Points: 
  • The facility will provide IC test, qualification, and test production services primarily for communications, automotive, IoT, and industrial applications.
  • Despite the recent world-wide economic challenges, at Presto, we are experiencing a high demand for new product industrialization and ramp production in Europe, said Michel Villemain, CEO, Presto Engineering.
  • This move to a modernized facility in Caen will enable us to support the growing customer demand.
  • Presto Engineering provides ASIC design and outsourced operations for semiconductor and IoT device companies, helping its customers minimize overhead, reduce risk, and accelerate time-to-market.

Si2 Announces 2020 Power of Partnerships Award Winners

Retrieved on: 
Monday, July 6, 2020
Electronic design automation, Engineering, Semiconductor, Technology, Manufacturing, Software, Hardware, Electronic engineering, Electrical engineering, Technology, Silicon Integration Initiative, Digital electronics, Si2, Integrated circuit design, Integrated circuit, UPM, Automation, Common Power Format

Semiconductor design experts from industry and academia are this years winners of the Silicon Integration Initiatives Power of Partnerships Award, recognizing the Si2 team that has made the most significant contributions to the field of electronic design automation.

Key Points: 
  • Semiconductor design experts from industry and academia are this years winners of the Silicon Integration Initiatives Power of Partnerships Award, recognizing the Si2 team that has made the most significant contributions to the field of electronic design automation.
  • Led by Jerry Frenkil, Si2 director of OpenStandards , members of the Unified Power Model Working Group are being honored for developing Si2 UPM, a system-level power modeling standard which helps designers describe, analyze, and control power consumption, critical factors in reducing overall design costs and increasing chip performance.
  • Frenkil said the working group has pioneered new methods for power modeling and analysis, leading to increased power efficiency.
  • Each Si2 coalition nominates one team for the annual Power of Partnerships award, which spotlights the essential role volunteers from Si2 member companies play in Si2s continuing success and value to the industry.

Panasonic Adopts Synopsys Custom Design Platform to Accelerate Next-Generation Automotive and Industrial Products

Retrieved on: 
Friday, May 22, 2020
Electronic design automation, Digital electronics, Integrated circuits, Electronic engineering, Hillsboro, Oregon, Synopsys, Parasitic extraction, Integrated circuit design, Spice, Mentor Graphics, EDA database, Magma Design Automation

Panasonic will use the Synopsys Custom Design Platform for all analog, mixed-signal and RF integrated circuit designs across a broad range of process technologies and applications

Key Points: 
  • Panasonic will use the Synopsys Custom Design Platform for all analog, mixed-signal and RF integrated circuit designs across a broad range of process technologies and applications
    Synopsys, Inc. (Nasdaq:SNPS) today announced that Panasonic Corporation has selected the Synopsys Custom Design Platform for its total design flow to develop next generation analog and mixed-signal products after the completion of a rigorous technical evaluation and successful migration of legacy design flows and data.
  • Panasonic has already begun design work with the Synopsys Custom Design Platform; it will be used by all Panasonic analog, mixed-signal and RF design groups world-wide.
  • Synopsys' Custom Design Platform is based on the Custom Compiler design and layout environment and includes HSPICE, FineSim SPICE, and CustomSim FastSPICE circuit simulation, Custom WaveView waveform display, StarRC parasitic extraction, and IC Validator physical verification.
  • Key features of the Custom Design Platform include reliability-aware verification, Extraction Fusion technology, and visually assisted layout.