Signoff

Cadence Extends Digital Design Leadership with Revolutionary ML-based Cerebrus, Delivering Best-in-class Productivity and Quality of Results

Retrieved on: 
Thursday, July 22, 2021

(Graphic: Business Wire)

Key Points: 
  • (Graphic: Business Wire)
    With the addition of Cerebrus to the broader digital product portfolio, Cadence offers the industrys most advanced ML-enabled digital full flow, from synthesis through implementation and signoff.
  • ML model reuse: Allows design learnings to be automatically applied to future designs, reducing the time to better results.
  • As part of our long-term partnership with Cadence, Samsung Foundry has used Cerebrus and the Cadence digital implementation flow on multiple applications.
  • Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

Cadence and UMC Collaborate on 22ULP/ULL Reference Flow Certification for Advanced Consumer, 5G and Automotive Designs

Retrieved on: 
Tuesday, July 13, 2021

The flow, which incorporates leading implementation and signoff technology for ultra-low power designs, enables mutual customers to deliver top-quality designs and achieve a faster path to tapeout.

Key Points: 
  • The flow, which incorporates leading implementation and signoff technology for ultra-low power designs, enables mutual customers to deliver top-quality designs and achieve a faster path to tapeout.
  • This certification allows UMC customers to leverage the most advanced low-power tool feature sets for synthesis, place-and-route, and signoff, enabling customers to design innovative applications with confidence.
  • For seven years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For.
  • Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

Ansys Multiphysics Solutions Achieve Certification for TSMC's N3 and N4 Process Technologies

Retrieved on: 
Tuesday, June 15, 2021

Ansys (NASDAQ: ANSS) achieved certification of its cutting-edge multiphysics signoff solutions for TSMC's advanced N3 and N4 process technologies.

Key Points: 
  • Ansys (NASDAQ: ANSS) achieved certification of its cutting-edge multiphysics signoff solutions for TSMC's advanced N3 and N4 process technologies.
  • The certification of Ansys RedHawk-SC for TSMC N3 and N4 process technologies includes power network extraction, power integrity and reliability, signal electromigration (EM), thermal reliability analysis for self-heat, thermal-aware EM and statistical EM budgeting.
  • Redhawk-SC will analyze very large 3nm network designs by using elastic compute, big-data analytics and high capacity of its underlyingAnsys SeaScapeinfrastructure.
  • "This collaboration with TSMC makes the signoff fidelity of our Ansys multiphysics simulation platform possible and Ansys remains committed to powering the best user experience for our joint customers."

Sequans Communications Adopts Cadence RF Solution to Develop Next-Generation 5G IoT Platform

Retrieved on: 
Thursday, June 10, 2021

Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that Sequans Communications S.A., a leader in 4G and 5G IoT solutions, has successfully adopted the Cadence Virtuoso RF Solution, including the Cadence Spectre X RF Simulator and Cadence EMX Planar 3D Solver, for high-frequency RF harmonic balance and electromagnetic (EM) analysis and signoff, to develop its next-generation 5G IoT platform.

Key Points: 
  • Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that Sequans Communications S.A., a leader in 4G and 5G IoT solutions, has successfully adopted the Cadence Virtuoso RF Solution, including the Cadence Spectre X RF Simulator and Cadence EMX Planar 3D Solver, for high-frequency RF harmonic balance and electromagnetic (EM) analysis and signoff, to develop its next-generation 5G IoT platform.
  • The comprehensive, full-suite solution from Cadence enabled Sequans engineers to achieve a 2X performance improvement versus its legacy solution and reduce time to market while ensuring a high level of accuracy.
  • The Sequans RF engineering team leveraged the VirtuosoRF Solution, which has a highly optimized design environment with embedded EM and multi-technology capabilities, to drive robust RF simulation and analyses.
  • Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

New Cadence Allegro X Design Platform Revolutionizes System Design

Retrieved on: 
Tuesday, June 8, 2021

Cadence Design Systems, Inc. (Nasdaq: CDNS) today debuted the Cadence Allegro X Design Platform, the industrys first engineering platform for system design that unifies schematic, layout, analysis, design collaboration and data management.

Key Points: 
  • Cadence Design Systems, Inc. (Nasdaq: CDNS) today debuted the Cadence Allegro X Design Platform, the industrys first engineering platform for system design that unifies schematic, layout, analysis, design collaboration and data management.
  • Built upon proven Allegro and OrCAD core technology, the new Allegro X platform revolutionizes and streamlines the system design process for engineersoffering unparalleled collaboration across all engineering disciplines, integration with best-in-class Cadence signoff-level simulation and analysis products, and greater layout performance.
  • View the full release here: https://www.businesswire.com/news/home/20210608005239/en/
    The Cadence Allegro X Design Platform is the industry's first engineering platform for system design that unifies schematic, layout, analysis, design collaboration and data management.
  • The Allegro X platform supports Cadences Intelligent System Design strategy, which enables customers to accelerate system innovation.

Synopsys Digital and Custom Design Platforms Certified for TSMC's Latest 3nm Process Technology

Retrieved on: 
Wednesday, May 26, 2021

Reference methodology benefits already validated across mutual-customer designs, increasing number of successful tapeouts

Key Points: 
  • Reference methodology benefits already validated across mutual-customer designs, increasing number of successful tapeouts
    Synopsys, Inc. (Nasdaq: SNPS )today announced that TSMC has certified Synopsys' digital and custom design solutions based on TSMC's latest design-rule manual (DRM) and process design kits for its advanced 3-nanometer (nm) process technology.
  • Additional signoff solutions certified for TSMC 3nm technology include NanoTime custom timing signoff, ESP custom equivalence verification and QuickCap NX parasitic field solver solution.
  • The Custom Compiler design and layout solution, part of the Synopsys Custom Design Platform, delivers improved productivity to designers using TSMC advanced process technologies.
  • Numerous enhancements to Custom Compiler, validated by early 3nm users including the Synopsys DesignWare IP team, reduce the effort to meet 3nm technology requirements.

Cadence Wins Four 2020 Samsung Foundry SAFE EDA Awards

Retrieved on: 
Tuesday, May 4, 2021

b'Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that it has received four 2020 SAFE EDA awards from Samsung Foundry.

Key Points: 
  • b'Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that it has received four 2020 SAFE EDA awards from Samsung Foundry.
  • \xe2\x80\x9cCadence delivered exemplary innovations last year, and the Samsung Foundry SAFE EDA awards were certainly well deserved.\xe2\x80\x9d\n\xe2\x80\x9cEnabling our customers to achieve design excellence is our top priority, and these awards from Samsung Foundry are indicative of our commitment to working closely with customers to reach their goals,\xe2\x80\x9d said Michael Jackson, corporate vice president, R&D in the Digital & Signoff Group at Cadence.
  • For seven years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For.
  • Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.\nView source version on businesswire.com: https://www.businesswire.com/news/home/20210504005012/en/\n'

Synopsys Introduces PrimeLib Unified Library Characterization and Validation Solution for Accelerated Access to Advanced Process Nodes

Retrieved on: 
Wednesday, April 21, 2021

The timely availability of quality signofflibraries for advanced process nodes are often a critical bottleneckfor chip designers, potentially delaying project schedules.

Key Points: 
  • The timely availability of quality signofflibraries for advanced process nodes are often a critical bottleneckfor chip designers, potentially delaying project schedules.
  • Synopsys\' next-generation PrimeLib library characterization solution will allow customers to leverage AWS for even higher levels of performance.
  • "\nSynopsys PrimeLib combines embedded Synopsys PrimeSim SPICE engine and signoff validation capabilities to produce PrimeTime golden signoff quality libraries.
  • "Synopsys PrimeLib library characterization and validation solution encapsulates differentiated technologies that will provide next-level performance, productivity and an accelerated path to silicon production.

Cadence Pegasus Verification System Certified for Samsung Foundry 5nm and 7nm Process Technologies

Retrieved on: 
Monday, April 19, 2021

b'Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that the Cadence\xc2\xae Pegasus\xe2\x84\xa2 Verification System has achieved certification for Samsung Foundry\xe2\x80\x99s 5nm and 7nm process technologies.

Key Points: 
  • b'Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that the Cadence\xc2\xae Pegasus\xe2\x84\xa2 Verification System has achieved certification for Samsung Foundry\xe2\x80\x99s 5nm and 7nm process technologies.
  • Samsung Foundry also delivered an enhanced, signoff-accurate process design kit (PDK) to facilitate the adoption of the Pegasus Verification System on the Samsung 5nm and 7nm technologies.\nThe Pegasus Verification System offers many advantages for engineers creating designs using Samsung\xe2\x80\x99s advanced nodes.
  • Additionally, the Pegasus Verification System features a tight, interactive integration with the Cadence Virtuoso\xc2\xae Layout Suite environment.
  • For more information on the Pegasus Verification System, please visit www.cadence.com/go/pegasusadvnd .\n\xe2\x80\x9cWe value our collaboration with Cadence and have worked diligently to enable our mutual customers to sign off their designs using the Pegasus Verification System and Samsung Foundry\xe2\x80\x99s advanced-node process technologies,\xe2\x80\x9d said Jong-Wook Kye, vice president of the Design Enablement Team at Samsung Electronics.

H3C Semiconductor and Ansys Innovate Next-Generation Network Processor Chip for High-end Routing, 5G Backhaul, AI and Cybersecurity Applications

Retrieved on: 
Wednesday, April 14, 2021

b'H3C Semiconductor designers used Ansys\' comprehensive multiphysics platform including Ansys SIwave, Ansys HFSS, and Ansys RedHawk-SC to engineer a state-of-the-art network processor chip featuring 56G Serdes and LPDDR5 interfaces\nUsing Ansys solutions, H3C Semiconductor designers managed multifaceted design issues from chip design to signoff, co-simulating the chip and package to power advanced routing, 5G backhaul, artificial intelligence (AI) and cybersecurity applications\nH3C Semiconductor leveraged Ansys (NASDAQ: ANSS) simulation solutions to launch ENGIANT 660, a highly sophisticated network processor chip that enables routing, AI, 5G backhaul and cybersecurity applications.

Key Points: 
  • b'H3C Semiconductor designers used Ansys\' comprehensive multiphysics platform including Ansys SIwave, Ansys HFSS, and Ansys RedHawk-SC to engineer a state-of-the-art network processor chip featuring 56G Serdes and LPDDR5 interfaces\nUsing Ansys solutions, H3C Semiconductor designers managed multifaceted design issues from chip design to signoff, co-simulating the chip and package to power advanced routing, 5G backhaul, artificial intelligence (AI) and cybersecurity applications\nH3C Semiconductor leveraged Ansys (NASDAQ: ANSS) simulation solutions to launch ENGIANT 660, a highly sophisticated network processor chip that enables routing, AI, 5G backhaul and cybersecurity applications.
  • Ansys solutions empowered designers to perform comprehensive analysis of power noise, signal integrity, thermal reliability and structural dependability from chip design to signoff.
  • This ensured the highly reliable processor chip met demanding design specifications and accelerated the development of chip, package and system.\nBy integrating Ansys simulations into their workflow, H3C Semiconductor designers cut hardware costs and substantially sped production of next-gen chips for routing, AI, 5G backhaul and cybersecurity applications.
  • "Collaborating with Ansys proved instrumental to our design team, which heavily relied on simulations to create ENGIANT 660, the first network processor chip independently developed by H3C Semiconductor.