Integrated circuit design

Siemens acquires Austemper Design Systems for breakthrough IC functional safety technology

Retrieved on: 
Friday, June 22, 2018
Engineering, Software engineering, Design, Safety, Electronic engineering, Car safety, ISO 26262, Functional safety, Reliability engineering, Mentor Graphics, Fault, Integrated circuit design

This technology allows customers to test and harden IC designs for functional safety in applications such as automotive, industrial and aerospace systems where functional safety and high reliability are mandatory for compliance to safety standards like ISO 26262.

Key Points: 
  • This technology allows customers to test and harden IC designs for functional safety in applications such as automotive, industrial and aerospace systems where functional safety and high reliability are mandatory for compliance to safety standards like ISO 26262.
  • ICs in these applications require three types of functional safety verification: for systemic faults, malicious faults and random hardware faults.
  • Mentor's existing Questa software is a leading technology for functional verification of systemic faults and provides solutions for verification of malicious faults for IC security.
  • The software technology from Austemper adds state-of-the-art safety analysis, auto-correction and fault simulation technology to address random hardware faults expanding on Mentor's existing functional safety leadership offerings of the Tessent product suite and the Veloce platform to provide the most complete end-to-end solution.

Mentor launches Calibre RealTime Digital to help cut weeks off of IC design signoff

Retrieved on: 
Monday, June 18, 2018
Electronic engineering, Electronics, Integrated circuits, Electromagnetism, Electronic design automation, Electronic design, Mentor Graphics, Signoff, Calibre, Integrated circuit design, Application-specific integrated circuit

WILSONVILLE, Ore., June 18, 2018 /PRNewswire/ --Mentor, a Siemens business, today announced Calibre RealTime Digital a new physical verification tool that works in concert with popular commercial place-and-route environments to ensure "Correct-by-Calibre" routing, and help design teams cut weeks off of IC signoff.

Key Points: 
  • WILSONVILLE, Ore., June 18, 2018 /PRNewswire/ --Mentor, a Siemens business, today announced Calibre RealTime Digital a new physical verification tool that works in concert with popular commercial place-and-route environments to ensure "Correct-by-Calibre" routing, and help design teams cut weeks off of IC signoff.
  • Calibre RealTime Digital is the sister product to Mentor's multi-award-winning Calibre RealTime Custom tool introduced in 2011 for custom IC design flows.
  • The new tool helps design teams solve a common problem in the last step of the design process.
  • The Calibre RealTime Digital tool helps solve these problems by working in concert with place-and-route tools.

Samsung's 8LPP process reference flow leverages Mentor Tessent tools for large design test-time savings

Retrieved on: 
Tuesday, May 22, 2018
Electronic engineering, Electronic design automation, Electromagnetism, Design, Electronic design, Digital electronics, Integrated circuits, Integrated circuit design, Application-specific integrated circuit, Integrated circuit, Register-transfer level, Design flow

These tools provide dramatic design and test time improvements for very large designs targeting markets such as mobile communications, high-speed network/server computing, cryptocurrency, and autonomous driving.

Key Points: 
  • These tools provide dramatic design and test time improvements for very large designs targeting markets such as mobile communications, high-speed network/server computing, cryptocurrency, and autonomous driving.
  • The Samsung Foundry Solutions reference flow includes TestKompress scan compression logic and Tessent ScanPro on-chip clock controllers automatically inserted early in the register transfer level (RTL) design stage.
  • Tessent TestKompress is used to create patterns at the core-level, early in the design flow as soon as the core design is ready.
  • The Tessent Diagnosis and Tessent YieldInsight tools are used to find systematic yield limiters and improve fabrication yields.