Design rule checking

GBT Automatic Correction of Integrated Circuits Connectivity Patent Application Received a Publication Notice

Retrieved on: 
Tuesday, July 11, 2023
DFM, Electronic design automation, DRC, Layout, LVS, EDA, Design, Research, Electronic, Patent, SAN, OTC, Artificial intelligence, Sigma, Integrated circuit, Silicon, Design rule checking, RF, Printed circuit board, RV

SAN DIEGO, July 11, 2023 (GLOBE NEWSWIRE) -- GBT Technologies Inc. (OTC PINK: GTCH ) ("GBT” or the “Company”), received a notice of publication for its continuation patent application for automatic correction of Integrated Circuits electrical connectivity mismatches, which the Company has assigned an internal code name Sigma. The application was published on June 23, 2023, publication number US-2023-0195995-A1. Sigma’s continuation application seeks to strengthen the invention’s AI technology, focusing on intelligent systems and methods to automate integrated circuits electrical connectivity errors correction. The patent application seeks to protect an EDA (Electronic Design Automation) technology that seeks to significantly accelerate the design time for integrated circuits as well as produce higher quality designs, particularly for advanced nanometer range of 5nm and below.

Key Points: 
  • SAN DIEGO, July 11, 2023 (GLOBE NEWSWIRE) -- GBT Technologies Inc. ( OTC PINK: GTCH ) ("GBT” or the “Company”), received a notice of publication for its continuation patent application for automatic correction of Integrated Circuits electrical connectivity mismatches, which the Company has assigned an internal code name Sigma.
  • Sigma’s continuation application seeks to strengthen the invention’s AI technology, focusing on intelligent systems and methods to automate integrated circuits electrical connectivity errors correction.
  • A mismatch in the microchip’s electrical connectivity means incorrect wiring between circuit’s components that may cause a malfunction or wrong functionalities.
  • GBT’s patent application describes an intelligent algorithmic system and method to perform automatic connectivity mismatches identification and correction while maintaining all other design aspects compliance.

GBT’s Automatic Correction of Integrated Circuits connectivity mismatches patent - Granted

Retrieved on: 
Tuesday, February 14, 2023
Automation, Patent, Sigma, Design rule checking, DFM, GBT, LVS, DRC, Research, Integrated circuit, IC, Design, RF, SAN, IP, Invention, Layout, AI, OTC, Printed circuit board, RV

SAN DIEGO, Feb. 14, 2023 (GLOBE NEWSWIRE) -- GBT Technologies Inc. (OTC PINK: GTCH ) ("GBT” or the “Company”), nonprovisional patent application for automatic correction of Integrated Circuits electrical connectivity mismatches, is expected to be granted on February 21, 2023. The patent number is 11,586,799. The patent protects an innovative software approach to automate integrated circuits electrical connectivity discrepancies correction with the goal of accelerating integrated circuits design time and producing higher quality designs, particularly for advanced nanometer range of 5nm and below. An electrical connectivity mismatch means erroneous wiring between the circuit’s components that may cause a malfunction or wrong functionalities. Especially in custom, semi-custom analog, mixed and RF layout styles, these corrections must be fixed manually which takes a significant amount of design time, which corrections may have further impact on area growth and introduce additional violations.

Key Points: 
  • SAN DIEGO, Feb. 14, 2023 (GLOBE NEWSWIRE) -- GBT Technologies Inc. ( OTC PINK: GTCH ) ("GBT” or the “Company”), nonprovisional patent application for automatic correction of Integrated Circuits electrical connectivity mismatches, is expected to be granted on February 21, 2023.
  • The patent protects an innovative software approach to automate integrated circuits electrical connectivity discrepancies correction with the goal of accelerating integrated circuits design time and producing higher quality designs, particularly for advanced nanometer range of 5nm and below.
  • An electrical connectivity mismatch means erroneous wiring between the circuit’s components that may cause a malfunction or wrong functionalities.
  • GBT’s patent describes an algorithmic systems and methods to perform an automatic connectivity correction with a click of a button.

GBT is Developing an Internet Based Licensing System to Potentially to Offer its Microchip Analysis Technology Through a Secured Web Portal Interface

Retrieved on: 
Tuesday, January 11, 2022
Forward-looking statement, IP, Technology, Research, IOT, SAN, DFM, Design, CAD, EDA, Internet of things, Connectivity, Electric Connection, Electronic design automation, GPS, GLOBE, IC, GBT, Design rule checking, U.S. Securities and Exchange Commission, OTC, Goal, Public policy, Artificial intelligence, Company, Environment, Electronic, AI, Internet, Software, Security (finance), Mobile phone, Risk management, Blockchain

SAN DIEGO, Jan. 11, 2022 (GLOBE NEWSWIRE) -- GBT Technologies Inc. ( OTC PINK:GTCH ) ("GBT or the Company), is developing an Internet based system to potentially license its microchip analysis technology through a web portal interface.

Key Points: 
  • SAN DIEGO, Jan. 11, 2022 (GLOBE NEWSWIRE) -- GBT Technologies Inc. ( OTC PINK:GTCH ) ("GBT or the Company), is developing an Internet based system to potentially license its microchip analysis technology through a web portal interface.
  • Using a secured portal, fabless IC design firms will be able to license and use GBTs IC analysis programs per demand.
  • This system will potentially offer an affordable solution for small and medium integrated design companies that cannot afford mass licensing model costs.
  • We plan to offer this type of licensing through a secured web portal that will provide time/user based, per-demand leasing option.

GBT Files Patent For ICs Layout Automatic Correction of Geometrical Design Rules System

Retrieved on: 
Tuesday, June 22, 2021
Electronic engineering, Digital electronics, Integrated circuits, Design, Electronic design automation, Electronic design, Integrated circuit layout, Design rule checking, TARGET

The patent protects IP for automatic correction of manufacturing process geometrical design rules violations in microchips layout data (Professional term; DRC).

Key Points: 
  • The patent protects IP for automatic correction of manufacturing process geometrical design rules violations in microchips layout data (Professional term; DRC).
  • Today, most of the design rule violations in the mask layout database are corrected manually by a layout designer, mainly with Analog and MIXED layout types.
  • In addition, geometrical design rules became more convoluted and highly complex to comply which requires vast amount of manual correction.
  • This type of system is a significant productivity enhancer tool within ICs design flow and will majorly reduce the global layout design time and chips overall time to market factor.

Deca collaborates with ASE and Siemens to launch APDK™ design methodology

Retrieved on: 
Thursday, March 18, 2021
Manufacturing, Industry economics), Secondary sector of the economy, Auschwitz concentration camp, Siemens, Design rule checking

The solution is the result of Decas collaboration with Advanced Semiconductor Engineering, Inc. (ASE) and Siemens Digital Industries Software.

Key Points: 
  • The solution is the result of Decas collaboration with Advanced Semiconductor Engineering, Inc. (ASE) and Siemens Digital Industries Software.
  • Each APDK bundles the full set of automation, design rules, DRC decks, and templates into a single package, offering a turn-key design flow.
  • Every design is jump-started by a library of templates, while extensive automation guides the designer from initial layout to Adaptive Patterning simulation, and finally through design sign-off using Siemens Calibre software.
  • Decas AP Studio modules integrate Adaptive Patterning design flows with EDA products from Siemens to provide an integrated design solution with a proven platform.

GBT Seeking to Develop New EDA Technology to Achieve Improved IC DFM (Design for Manufacturing)

Retrieved on: 
Thursday, March 18, 2021
Design, Electronic engineering, Integrated circuits, Electronic design automation, Electrical engineering, Mechanical engineering, Design rule checking, Design for manufacturability, Integrated circuit design

SAN DIEGO, March 18, 2021 (GLOBE NEWSWIRE) -- GBT Technologies Inc. ( OTC PINK:GTCH ) ("GBT or the Company), is seeking to develop a new EDA (Electronic Design Automation) technology to achieve ICs better DFM (Design For Manufacturing) analysis.

Key Points: 
  • SAN DIEGO, March 18, 2021 (GLOBE NEWSWIRE) -- GBT Technologies Inc. ( OTC PINK:GTCH ) ("GBT or the Company), is seeking to develop a new EDA (Electronic Design Automation) technology to achieve ICs better DFM (Design For Manufacturing) analysis.
  • The EDA R&D efforts will be concentrating on DFM rules analysis, physical layout geometrical rules (DRC) and nanometer silicon modeling.
  • GBT already started to address a key dependency between manufacturing and IC design; the Design Rule Check (DRC) aspect.
  • GBT envisions this system as a creation of a global mesh network using advanced nodes and super performing new generation IC technology.

GBT Commenced Design Productivity Software Solutions Development

Retrieved on: 
Monday, November 2, 2020
Integrated circuits, Electrical engineering, Digital electronics, Electronic engineering, Electronic design, Integrated circuit design, Design rule checking, DEC Alpha, Physical design

SAN DIEGO, Nov. 02, 2020 (GLOBE NEWSWIRE) -- GBT Technologies Inc. (OTC PINK: GTCH) ("GBT, or the Company) announced that GBT together with Alpha EDA (Alpha), its joint venture partner, have developed IC design productivity enhancement algorithms and methods.

Key Points: 
  • SAN DIEGO, Nov. 02, 2020 (GLOBE NEWSWIRE) -- GBT Technologies Inc. (OTC PINK: GTCH) ("GBT, or the Company) announced that GBT together with Alpha EDA (Alpha), its joint venture partner, have developed IC design productivity enhancement algorithms and methods.
  • The geometrical/physical design rules of the tiny transistors are becoming a bottleneck when it comes to achieving reasonable chips design time.
  • In addition, Alpha's productivity solutions address electrical rules violations in order to maintain chip's power efficiency, high reliability, and high performance operation.
  • Economy condition enforces IC design houses to move to more cost-effective design processes in order to stay in business.

Breakthrough Synopsys IC Validator Technologies Deliver Faster Physical Signoff Convergence

Retrieved on: 
Tuesday, October 20, 2020
Digital electronics, Electronic design automation, Electronic engineering, Integrated circuits, Design rule checking, Design, Signoff, Synopsys, DRC

IC Validator's unique elastic CPU management technology delivers up to 40 percent compute savings in physical signoff for both on-premise and cloud environments.

Key Points: 
  • IC Validator's unique elastic CPU management technology delivers up to 40 percent compute savings in physical signoff for both on-premise and cloud environments.
  • Another new technology in IC Validator includes machine-learning driven root cause analysis that automatically identifies critical design rule checking (DRC) issues enabling faster DRC closure.
  • Architected for high performance and scalability, IC Validator maximizes mainstream hardware utilization, using smart memory-aware load scheduling and balancing technologies.
  • IC Validator verification in Synopsys' Fusion Design Platform enables fast DRC checking, automatic fixing, timing aware fill insertion and signoff accurate STAR RC integration to accelerate convergence.

Cadence Pegasus Verification System Certified for TSMC N16, N12 and N7 Process Technologies

Retrieved on: 
Thursday, October 8, 2020
Semiconductor, Hardware, Electronic design automation, Technology, Software, Companies, Digital electronics, Electronic engineering, TSMC, Cadence Design Systems, Signoff, Design rule checking, Fabless semiconductor companies

Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that the Pegasus Verification System has achieved the latest Design Rule Manual (DRM) certification for the TSMC N16, N12 and N7 process technologies.

Key Points: 
  • Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that the Pegasus Verification System has achieved the latest Design Rule Manual (DRM) certification for the TSMC N16, N12 and N7 process technologies.
  • The Cadence Pegasus Verification System has been successfully validated by TSMC to provide customers with a fast path to meet physical verification signoff goals across several application areas including AI, automotive, processor, data center and IP applications.
  • We worked closely with Cadence to deliver this certified Pegasus Verification System across several advanced TSMC processes, said Suk Lee, senior director of Design Infrastructure Management Division at TSMC.
  • Our continued collaboration with TSMC on the Pegasus Verification System certification provides customers with confidence that they can attain consistent, accurate results and meet competitive schedules.

The MOSIS Service Selects Synopsys' IC Validator for Large-scale FinFET SoCs

Retrieved on: 
Thursday, July 11, 2019
Electronic engineering, Digital electronics, Integrated circuits, Electronics, Semiconductor device fabrication, MOSIS, Signoff, Design rule checking, Synopsys, Layout Versus Schematic, Integrated circuit layout, Physical verification

Synopsys, Inc. (Nasdaq:SNPS) today announced that The MOSIS Service, a leading provider of Multi-Project Wafers, has selected Synopsys' IC Validator tool for physical verification signoff.

Key Points: 
  • Synopsys, Inc. (Nasdaq:SNPS) today announced that The MOSIS Service, a leading provider of Multi-Project Wafers, has selected Synopsys' IC Validator tool for physical verification signoff.
  • IC Validator's feature-rich physical verification solution, coupled with a highly scalable engine, has allowed The MOSIS Service to achieve significantly faster physical signoff.
  • The MOSIS Service deployed IC Validator for full-chip design rule checking (DRC) and layout-versus-schematic (LVS) signoff on designs in FinFET process technologies.
  • "The MOSIS Service processes designs for a high volume of multi-project wafers that speed production and reduce costs for our customers.