Integrated circuit design

57th Design Automation Conference Names Executive Committee for the 2020 Conference and Exhibition

Retrieved on: 
Wednesday, September 25, 2019
Technology, Semiconductor, Telecommunications, Software, Networks, Internet, Hardware, Electronic design automation, Electronic engineering, IEEE conferences, Electronics, Electrical engineering, Electronic design, Design Automation Conference, Electronic design automation, Cadence Design Systems, Mentor Graphics, Integrated circuit design, Silicon Integration Initiative, Draft:Antun Domic

The Design Automation Conference (DAC) , the only event devoted to electronic design and design automation of electronic circuits and systems, has named Dr. Zhuo Li, Group Director of Cadence Design Systems as the 57th DAC General Chair.

Key Points: 
  • The Design Automation Conference (DAC) , the only event devoted to electronic design and design automation of electronic circuits and systems, has named Dr. Zhuo Li, Group Director of Cadence Design Systems as the 57th DAC General Chair.
  • A diverse group of volunteers has been selected from across the semiconductor, design, research, embedded systems, intellectual property and electronic design automation (EDA) industries to join the 2020 EC.
  • The Design Automation Conference (DAC) is recognized as the premier event for the design of electronic circuits and systems, and for electronic design automation (EDA) and silicon solutions.
  • Design Automation Conference acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

ESD Alliance Reports EDA Industry Revenue Increase for Q2 2019

Retrieved on: 
Tuesday, September 17, 2019
Electronic engineering, Milpitas, California, Silicon Valley, Q2, Electronic design automation, EDA, Integrated circuit design, Geography of California, Technology, California

MILPITAS, Calif., Sept. 17, 2019 (GLOBE NEWSWIRE) -- The Electronic System Design (ESD) Alliance Market Statistics Service (MSS) today announced that the Electronic Design Automation (EDA) industry revenue increased 6.6 percent for Q2 2019 to $2472.1 million, compared to $2318.5 million in Q2 2018.

Key Points: 
  • MILPITAS, Calif., Sept. 17, 2019 (GLOBE NEWSWIRE) -- The Electronic System Design (ESD) Alliance Market Statistics Service (MSS) today announced that the Electronic Design Automation (EDA) industry revenue increased 6.6 percent for Q2 2019 to $2472.1 million, compared to $2318.5 million in Q2 2018.
  • IC Physical Design & Verification revenue was $500.1 million in Q2 2019, a 7.1 percent increase compared to Q2 2018.
  • Semiconductor Intellectual Property (SIP) revenue totaled $835 million in Q2 2019, a 19.7 percent increase compared to Q2 2018.
  • The ESD Alliance Market Statistics Service reports EDA industry revenue data quarterly and is available to Alliance members.

North America Electronic Design Automation Markets Report 2018-2019 & 2027 - ResearchAndMarkets.com

Retrieved on: 
Monday, September 16, 2019
Semiconductor, Electronic design automation, Technology, Software, Electronic engineering, Electrical engineering, Electronics, Electromagnetism, Industries, Semiconductor device fabrication, Semiconductor industry, Automation, Electronic design automation, Integrated circuit design

The "North America Electronic Design Automation Market to 2027 - Regional Analysis and Forecasts by Type and Application" report has been added to ResearchAndMarkets.com's offering.

Key Points: 
  • The "North America Electronic Design Automation Market to 2027 - Regional Analysis and Forecasts by Type and Application" report has been added to ResearchAndMarkets.com's offering.
  • The North America electronic design automation market accounted for US$ 4.10 Bn in 2018 and is expected to grow at a CAGR of 10.2% over the forecast period 2019-2027, to account for US$ 9.70 Bn in 2027.
  • The significant growth of the semiconductor industry is anticipated to boost the electronic design automation market growth.
  • Moreover, the increased focus on miniaturization of electronic devices is expected to boost the electronic design automation market growth in the forecast period.

sureCore Unveils Low Power Design Service

Retrieved on: 
Tuesday, August 27, 2019
Electronic design, Design, Electronics, Integrated circuits, Electronic engineering, Integrated circuit design, Mentor Graphics, Mixed-signal integrated circuit

SHEFFIELD, England, Aug. 27, 2019 /PRNewswire/ --sureCore Limited today announced that it has opened a new Low Power Design Service that offers its concept-to-tape-out low power mixed-signal design expertise to ASIC developers.

Key Points: 
  • SHEFFIELD, England, Aug. 27, 2019 /PRNewswire/ --sureCore Limited today announced that it has opened a new Low Power Design Service that offers its concept-to-tape-out low power mixed-signal design expertise to ASIC developers.
  • sureCore's Design Service targets the pervasive system-centric low-powerdesign challenge through a comprehensive suite of low-power mixed signal services, including design and layout capabilities, technology porting,as well as low voltage verification and characterization.
  • sureCore is the low power innovator who empowers the IC design community to meet their aggressive power budgets through a portfolio of, ultra-low power memory design services and standard products.
  • sureCore's low-power engineering methodologies and design flows meet the most exacting memory requirements with customized low-power SRAM IP and low power mixed signal design services that create clear market differentiation.

Cadence and UMC Collaborate on Certification of Analog/Mixed-Signal Flow for 28HPC+ Process

Retrieved on: 
Tuesday, August 6, 2019
Electronic design automation, Semiconductor, Technology, Software, Hardware, Electronic engineering, Electronics, Design, Cadence Design Systems, Electronic design, Mentor Graphics, Integrated circuit design, Digital electronics, Sigrity, Cadence, UMC

Cadence Design Systems, Inc. (NASDAQ: CDNS) and United Microelectronics Corporation (NYSE: UMC; TWSE: 2303) ("UMC"), a leading global semiconductor foundry, today announced that the Cadence analog/mixed-signal (AMS) IC design flow has achieved certification for UMCs 28HPC+ process technology.

Key Points: 
  • Cadence Design Systems, Inc. (NASDAQ: CDNS) and United Microelectronics Corporation (NYSE: UMC; TWSE: 2303) ("UMC"), a leading global semiconductor foundry, today announced that the Cadence analog/mixed-signal (AMS) IC design flow has achieved certification for UMCs 28HPC+ process technology.
  • The Cadence AMS flow incorporates the proven custom/analog, digital and verification platforms, and supports the broader Cadence Intelligent System Design strategy, accelerating SoC design excellence.
  • For more information on the Cadence AMS flow that supports the UMC 28HPC+ process technology, visit www.cadence.com/go/UMC28HPCp .
  • Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

Cadence and UMC Collaborate on Certification of Analog/Mixed-Signal Flow for 28HPC+ Process

Retrieved on: 
Tuesday, August 6, 2019
Electronic design automation, Semiconductor, Technology, Telecommunications, Mobile, Wireless, Electronic engineering, Electronics, Design, Cadence Design Systems, Electronic design, Mentor Graphics, Integrated circuit design, Digital electronics, Sigrity, Cadence, UMC

Cadence Design Systems, Inc. (NASDAQ: CDNS) and United Microelectronics Corporation (NYSE: UMC; TWSE: 2303) ("UMC"), a leading global semiconductor foundry, today announced that the Cadence analog/mixed-signal (AMS) IC design flow has achieved certification for UMCs 28HPC+ process technology.

Key Points: 
  • Cadence Design Systems, Inc. (NASDAQ: CDNS) and United Microelectronics Corporation (NYSE: UMC; TWSE: 2303) ("UMC"), a leading global semiconductor foundry, today announced that the Cadence analog/mixed-signal (AMS) IC design flow has achieved certification for UMCs 28HPC+ process technology.
  • The Cadence AMS flow incorporates the proven custom/analog, digital and verification platforms, and supports the broader Cadence Intelligent System Design strategy, accelerating SoC design excellence.
  • For more information on the Cadence AMS flow that supports the UMC 28HPC+ process technology, visit www.cadence.com/go/UMC28HPCp .
  • Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

The electronic design automation (EDA) tools market was valued at USD 6.32 billion in 2018, and is projected to reach USD 9.49 billion by 2024, registering a CAGR of 7.8%, during the forecast period (2019

Retrieved on: 
Monday, July 15, 2019
Electronic engineering, Electronics, Electrical engineering, Electronic design, Electronic design automation, Mentor Graphics, Integrated circuit design, EDA

The electronic design automation (EDA) tools market was valued at USD 6.32 billion in 2018, and is projected to reach USD 9.49 billion by 2024, registering a CAGR of 7.8%, during the forecast period (2019-2024).

Key Points: 
  • The electronic design automation (EDA) tools market was valued at USD 6.32 billion in 2018, and is projected to reach USD 9.49 billion by 2024, registering a CAGR of 7.8%, during the forecast period (2019-2024).
  • Electronic design automation (EDA) tools have provided the silicon industry with the ability to innovate over the past few years.
  • The booming automotive, IoT, and AI sectors drive the growth of the semiconductor market, which requires electronic devices with complex designs.
  • Electronic design automation (EDA) is a term for a category of software products and processes that help to design electronic systems with the aid of computers.

TowerJazz, Cadence and Lumerical Deliver Silicon-Photonics and SiGe- Integrated PDK with a Complete Optical Transceiver Design Environment

Retrieved on: 
Wednesday, July 10, 2019
Digital electronics, Electronic engineering, Electronics, Electronic design automation, Tower Semiconductor, Logic design, Cadence, PDK, Simulation, Mentor Graphics, Integrated circuit design, Logic simulation

The differentiated PDK is based on the Cadence Virtuoso custom IC design platform, providing native synthesis using the Cadence CurvyCore engine and Electrical-Optical co-simulation capability in Lumerical's photonic integrated circuit simulator INTERCONNECT.

Key Points: 
  • The differentiated PDK is based on the Cadence Virtuoso custom IC design platform, providing native synthesis using the Cadence CurvyCore engine and Electrical-Optical co-simulation capability in Lumerical's photonic integrated circuit simulator INTERCONNECT.
  • "This new capability enables our mutual customers to shortcut development cycles and accelerate the introduction of 400Gb and 800Gb breakthrough products."
  • Delivery of the new TowerJazz PDK encompasses the previously available Lumerical Compact Model Library (CML) to enable a proven, complete solution incorporating co-simulation utilizing industry leading tools.
  • "TowerJazz and Cadence customers can begin leveraging the high-performance shape generation technology within the Virtuoso design environment to further advance the development of complete multi-chip photonics systems," said Glen Clark, Vice President, Research and Development at Cadence.

Lumerical 2019b Release Delivers Dramatically Faster Time-to-results for Photonic Designers

Retrieved on: 
Thursday, June 6, 2019
Hardware description languages, Electronic engineering, Electronics, Electrical engineering, Verilog, Integrated circuit design

Lumerical continues to push the innovation envelope to deliver accurate, high-performance simulators in easy-to-use design environments specifically targeted at photonic designers.

Key Points: 
  • Lumerical continues to push the innovation envelope to deliver accurate, high-performance simulators in easy-to-use design environments specifically targeted at photonic designers.
  • In this 2019b release, Lumerical delivers powerful capabilities that speed time-to-results for photonics designers.
  • With the 2019b release, Lumerical further establishes itself as the industry leader in Verilog-A photonic compact models by delivering an improved CML Compiler that performs automated QA on the Verilog-A models it produces.
  • The set of Verilog-A models supported continues to expand, with the addition of thermo-optic phase shifters in the 2019b release.

Faraday Adopts Synopsys SpyGlass Design Handoff Kit to Ensure High Design Quality

Retrieved on: 
Wednesday, June 5, 2019
Electronic engineering, Electronics, Technology, Hardware acceleration, Electronic design, Integrated circuits, Integrated circuit design, Michael Faraday, System on a chip, Handover, Faraday, Application-specific integrated circuit

Faraday has deployed the SpyGlass Design Handoff Kit to ensure ASIC designs meet design quality requirements before initiating ASIC design service and production.

Key Points: 
  • Faraday has deployed the SpyGlass Design Handoff Kit to ensure ASIC designs meet design quality requirements before initiating ASIC design service and production.
  • The software and methodologies needed to implement Faraday's IP and system-on-chip (SoC) design qualification requirements will also be integrated into the SpyGlass Design Handoff Kit.
  • "Faraday is using the SpyGlass Design Handoff Kit to guarantee design quality at handoff from IP providers and customers, reducing errors and iterations before ASIC production and accelerating time-to-market for our customers."
  • Faraday requires IP providers and customers to validate their designs with the SpyGlass Design Handoff Kit to ensure a minimum level of completeness before handoff.