Verilog

Accellera Systems Initiative Honors Shalom Bresticker with First Distinguished Service Award

Retrieved on: 
Tuesday, February 27, 2024
Dai, ELK, OVL, Verilog, SystemVerilog, Electronics, Distinguished Service Award, Verilog-AMS, Princeton University, Documentation, EDA, Knowledge, IEEE, Lady Davis Fellows, Nursing

ELK GROVE, Calif., Feb. 27, 2024 (GLOBE NEWSWIRE) -- Accellera Systems Initiative (Accellera) announced today that Shalom Bresticker, a longtime friend and contributor to Accellera standards efforts, is honored with the first Distinguished Service Award.

Key Points: 
  • ELK GROVE, Calif., Feb. 27, 2024 (GLOBE NEWSWIRE) -- Accellera Systems Initiative (Accellera) announced today that Shalom Bresticker, a longtime friend and contributor to Accellera standards efforts, is honored with the first Distinguished Service Award.
  • Mr. Bresticker has been an electronics engineer for 30 years and more recently a technical editor for nearly a decade.
  • He was awarded the Accellera Technical Excellence Award in 2010 for his contributions to the Verilog, SystemVerilog, Verilog-AMS and OVL standards.
  • “Shalom has been an invaluable contributor to the development of Accellera standards,” stated Lu Dai, Accellera Chair.

INDUSTRY LEADING PPA DSP AVAILABLE FOR ALL EXISTING EFLX EFPGA

Retrieved on: 
Wednesday, March 6, 2024
Compiler, Simulink, TPU, Verilog, Silicon, Macs, Complex, FFT, IP, DSP, FPGA

MOUNTAIN VIEW, Calif., March 6, 2024 /PRNewswire/ -- Flex Logix® Technologies, Inc., the leading supplier of embedded FPGA (eFPGA) IP and reconfigurable DSP/AI solutions, announced today that InferX DSP is in development for use with existing EFLX eFPGA from 40nm to 7nm.

Key Points: 
  • MOUNTAIN VIEW, Calif., March 6, 2024 /PRNewswire/ -- Flex Logix® Technologies, Inc. , the leading supplier of embedded FPGA (eFPGA) IP and reconfigurable DSP/AI solutions, announced today that InferX DSP is in development for use with existing EFLX eFPGA from 40nm to 7nm.
  • One, two, four, eight or 16 TPUs can be controlled by existing EFLX eFPGA from 40nm to 7nm.
  • "InferX with existing EFLX eFPGA allows us to deliver much higher DSP throughput at much lower cost than eFPGA with MACs.
  • Benchmarks are available for all of the process nodes we have silicon for now: 40, 28, 22, 16, 12, 7nm.

Industry Veterans Atiq Raza and Prabhu Goel Join minds.ai Board of Directors

Retrieved on: 
Tuesday, October 24, 2023
CHIPS, 2020 North Macedonian parliamentary election, Gateway Design Automation, European Chips Act, AMD, Automation, Artificial intelligence, Learning, Growth, Verilog, Maestro, Deep learning, IBM, Management, Cryptocurrency

SANTA CRUZ, Calif., Oct. 24, 2023 /PRNewswire/ -- minds.ai announced today that Atiq Raza and Prabhu Goel have joined the board of directors, bringing decades of experience in the semiconductor industry to the company. Their expertise will help guide the company as it expands deployment of its minds.ai Maestro™ solution to optimize semiconductor production while slashing manufacturing cost and waste.

Key Points: 
  • SANTA CRUZ, Calif., Oct. 24, 2023 /PRNewswire/ -- minds.ai announced today that Atiq Raza and Prabhu Goel have joined the board of directors, bringing decades of experience in the semiconductor industry to the company.
  • Goel is a managing partner at Green Span Ventures and at Goel Family Ventures, which invest in enterprise software and renewable energy.
  • Atiq Raza, executive board chair, minds.ai, said: "The reason I leaned in at minds.ai is the impression made on me regarding the amazing talent of the team.
  • Prabhu Goel, board member, minds.ai, said: "As an active venture investor, I'm always looking for innovative ideas.

Efabless Launches 3rd AI-Generated Open-Source AI Contest to Extend the Caravel SoC Platform with AI-Generated Peripherals

Retrieved on: 
Monday, September 25, 2023
Bard, RTL, ChatGPT, PALO, Boat, Caravel, Creativity, Documentation, GDS, Verilog, AI, Automation, Copper, Medical device

PALO ALTO, Calif., Sept. 25, 2023 (GLOBE NEWSWIRE) -- Efabless Corporation, the creator platform for chips, is excited to announce the launch of its 3rd AI-Generated Open-Source AI Contest.

Key Points: 
  • PALO ALTO, Calif., Sept. 25, 2023 (GLOBE NEWSWIRE) -- Efabless Corporation, the creator platform for chips, is excited to announce the launch of its 3rd AI-Generated Open-Source AI Contest.
  • This unique competition invites participants to utilize generative AI tools such as chatGPT, Bard, or similar, to generate open-source silicon designs.
  • The Efabless SoC platform is called “Caravel” – after the small but fast and maneuverable sailing ships built in Spain and Portugal starting in the 15th century.
  • The theme for this contest, “Float the Boat,” plays off of the platform name and focuses on extending the Caravel SoC with useful and verified AI-generated peripherals.

FLEX LOGIX ANNOUNCES RECONFIGURABLE BLOCK RAM WITH ECC OPTION

Retrieved on: 
Monday, September 18, 2023
ECC, Urinary tract infection, Reconfigurable computing, Correction, Parity, IP, Ticketmaster, LLC v. RMG Technologies, Inc., Computer data storage, Verilog

MOUNTAIN VIEW, Calif.,  Sept. 18, 2023 /PRNewswire/ --  Flex Logix® Technologies, Inc., the leading supplier of eFPGA IP, announced today the availability of Reconfigurable Block RAM with ECC and Parity Options.

Key Points: 
  • MOUNTAIN VIEW, Calif., Sept. 18, 2023 /PRNewswire/ -- Flex Logix® Technologies, Inc ., the leading supplier of eFPGA IP, announced today the availability of Reconfigurable Block RAM with ECC and Parity Options.
  • "Our customers want Block RAM (BRAM) that is flexible.
  • BRAM access can be configured for single port or two port or true dual port," said Geoff Tate, CEO of Flex Logix.
  • Now we have a single Reconfigurable Block RAM that can meet all of these needs."

Efabless Design Challenge Winners Advance the Power of AI in Chip Design

Retrieved on: 
Wednesday, September 13, 2023
Crypto, Learning, RTL, Integrated circuit, Challenge, PALO, Synthetic media, ChatGPT, IC, SOC, Caravel, CNN, Convolutional neural network, Documentation, TensorFlow, Data, Generative, AI, First Ever, MNIST, Medical device, Verilog

PALO ALTO, Calif., Sept. 13, 2023 (GLOBE NEWSWIRE) -- Efabless Corporation, the creator platform for chips, today announced the first, second, and third-place winners of its Second AI Generated Open-Source Silicon Design Challenge.

Key Points: 
  • PALO ALTO, Calif., Sept. 13, 2023 (GLOBE NEWSWIRE) -- Efabless Corporation, the creator platform for chips, today announced the first, second, and third-place winners of its Second AI Generated Open-Source Silicon Design Challenge.
  • The AI Generated Open-Source Silicon Design Challenges are a part of Efabless’ initiative to democratize the use of Generative AI for chip design.
  • The initiative drives innovation and learning in the chip design community by:
    Advancing the capabilities of generative AI use for chip design and verification, as well as secure device implementation.
  • The Verilog designs are then implemented using the chipIgnite Caravel SoC template and an open-source design flow such as OpenLane.

Tachyum Offers Its TPU Inference IP to Edge and Embedded Markets

Retrieved on: 
Tuesday, September 12, 2023
Semiconductor, Hardware, Data Management, Technology, Artificial Intelligence, RTL, TAI, Internet of things, IP, TPU, CAPEX, HPC, Experiential learning, Artificial intelligence, Prodigy, Architecture, OPEX, AI, Universal, Economics, GPU, Medical device, Verilog

Tachyum ® today announced that it is expanding the unique value proposition of its Tachyum Prodigy by offering its Tachyum TPU® (Tachyum Processing Unit) intellectual property as a licensable core, allowing developers to take full advantage of intelligent, datacenter-trained AI when making IoT and Edge devices.

Key Points: 
  • Tachyum ® today announced that it is expanding the unique value proposition of its Tachyum Prodigy by offering its Tachyum TPU® (Tachyum Processing Unit) intellectual property as a licensable core, allowing developers to take full advantage of intelligent, datacenter-trained AI when making IoT and Edge devices.
  • With the tremendous growth of the AI chipset market for edge inference, Tachyum is looking to extend its proprietary Tachyum AI data type beyond the datacenter by providing its internationally registered and trademarked IP to outside developers.
  • Key features of the TPU inference and generative AI/ML IP architecture include architectural transactional and cycle accurate simulators; tools and compilers support; and hardware licensable IP, including RTL in Verilog, UVM Testbench and synthesis constraints.
  • For licensing opportunities of Tachyum’s TPU IP, interested vendors are invited to contact the company at https://www.tachyum.com/contact/ .

Efabless Corporation Launches Its Second AI-Generated Chip Design Contest

Retrieved on: 
Thursday, July 6, 2023
IC, Silicon, AI, PALO, LLM, Verilog, Medical device

The second challenge will extend the design time to two months to enable wider participation, more learnings, and more success.

Key Points: 
  • The second challenge will extend the design time to two months to enable wider participation, more learnings, and more success.
  • The Efabless AI Generated Open-Source Silicon Design Challenge series engages a global community in LLM AI chip creation to demonstrate the state of the art over time.
  • "We are excited to launch the second AI Generated Open-Source Silicon Design Challenge," said Mike Wishart, CEO of Efabless.
  • To learn more about the second AI Generated Open-Source Silicon Design Challenge, please visit https://efabless.com/ai-generated-design-contest-2 .

Efabless Reveals Winners of AI-Generated Silicon Design Challenge

Retrieved on: 
Thursday, June 8, 2023
Learning, Chip Chats, Model predictive control, MPC, PALO, NYU, ChatGPT, Tsinghua-Berkeley Shenzhen Institute, Silicon, Documentation, CPU, PIO, Behavior, Medical device, Video game, MATLAB, New York University, Verilog

PALO ALTO, Calif., June 08, 2023 (GLOBE NEWSWIRE) -- Efabless Corporation, the creator platform for chips, today announced the winners of its AI Generated Open-Source Silicon Design Challenge. The challenge invited participants to use generative AI to design and tapeout an open-source silicon chip and to do so in three weeks. The wide range of participants and the variety of innovative designs showed how generative AI can accelerate and democratize innovation in chips.

Key Points: 
  • PALO ALTO, Calif., June 08, 2023 (GLOBE NEWSWIRE) -- Efabless Corporation, the creator platform for chips, today announced the winners of its AI Generated Open-Source Silicon Design Challenge .
  • The challenge invited participants to use generative AI to design and tapeout an open-source silicon chip and to do so in three weeks.
  • This design is a RISC-V CPU, implemented with Verilog code produced via a series of prompts given to ChatGPT-4.
  • Efabless will now fabricate the three winning designs on its chipIgnite shuttle with the winners receiving packaged parts and evaluation boards - a value of $9,750.

Efabless Announces AI Generated Open-Source Silicon Design Challenge

Retrieved on: 
Friday, May 19, 2023
Generative, Synthetic media, ChatGPT, Silicon, AI, RTL, SOC, GDS, Caravel, Verilog, PALO, Auction, Medical device

Participants will utilize generative AI to design a silicon chip and earn a chance to win fabrication, packaged parts and evaluation boards at no cost

Key Points: 
  • Participants will utilize generative AI to design a silicon chip and earn a chance to win fabrication, packaged parts and evaluation boards at no cost
    Deadline to enter is midnight on June 2, 2023
    PALO ALTO, Calif., May 19, 2023 (GLOBE NEWSWIRE) -- Efabless Corporation today announced its AI Generated Open-Source Silicon Design Challenge which provides a hands-on opportunity to experience how simple it can be to use AI to create and tapeout chip designs in days or even hours.
  • First, it will demonstrate the potential of Generative AI to accelerate chip innovation by simplifying design and doing it faster and for less cost.
  • Generative AI offers the potential to revolutionize chip design by automating many of the time-consuming tasks involved in the process.
  • In this challenge, participants will use Generative AI (e.g., chatGPT, Bard or similar) to generate Verilog from natural language prompts.