VLIW

CEVA Announces its Most Powerful and Efficient DSP Architecture to Date, Addressing the Massive Compute Requirements of 5G-Advanced and Beyond

Retrieved on: 
Thursday, February 23, 2023
Congress, Digital, CEVA, ASIC, Research, Silicon, Architecture, CPU, VLIW, Environment, 5G, RAN, OEM, SOC, DVT, Tier 1, Industrial, DSP, Mobile phone, DSPS

BARCELONA, Spain, Feb. 23, 2023 /PRNewswire/ -- Mobile World Congress CEVA, Inc. (NASDAQ: CEVA), the leading licensor of wireless connectivity and smart sensing technologies and co-creation solutions, today announced its 5th generation CEVA-XC DSP architecture and its most efficient to date, the CEVA-XC20.

Key Points: 
  • base stations, virtualized DU accelerators, and beamforming compute in Massive MIMO radios).
  • Our latest CEVA-XC20 DSP architecture addresses these challenges, leveraging more than 30 years of expertise in cellular DSPs at CEVA to deliver incredible power efficiency for the most intense baseband compute use cases.
  • The first core based on the CEVA-XC20 architecture is the CEVA-XC22 DSP, supporting two execution threads using the groundbreaking DVT scheme.
  • CEVA-XC22 customers can also benefit from ASIC/SoC co-creation services by CEVA's Intrinsix team to help integrate and support system design and modem development.

CEVA Joins Intel Pathfinder for RISC-V Program

Retrieved on: 
Thursday, December 1, 2022
Semiconductor, Interrupt, Human, IP, KWS, Image, VLIW, Ultra, Strategy, SIMD, Real, Wi-Fi, Socs, Macs, AI, Television, MAC, Pathfinder, DSPS, Intel, UWB, GNSS, AVS, ISA, IOT, Language, NB, LLVM, Marketing, IPS, Robotics, PC, 4-way, DSP, Monolithic kernel, CEVA, Research, Ecosystem, Name, Hillcrest Labs, Intelligence, AR, Original equipment manufacturer, Algorithm, Mobile phone, Cassette tape, Bluetooth

ROCKVILLE, Md., Dec. 1, 2022 /PRNewswire/ -- CEVA, Inc. (NASDAQ: CEVA), the leading licensor of wireless connectivity and smart sensing technologies and co-creation solutions, today announced that it will make its CEVA-BX1 and CEVA-BX2 Audio DSPs and audio front-end software stack available for commercial developers through the Intel® Pathfinder for RISC-V* ecosystem. A Strategic Member of RISC-V International, CEVA is making its industry leading audio DSPs and software stack accessible for prototyping and production design through the Intel® FPGA based pre-silicon development platform.

Key Points: 
  • A Strategic Member of RISC-V International, CEVA is making its industry leading audio DSPs and software stack accessible for prototyping and production design through the Intel FPGA based pre-silicon development platform.
  • "We are thrilled to make our CEVA-BX Audio DSPs and audio front-end software IP available for customers developing with Intel Pathfinder for RISC-V," said Moshe Sheier, Vice President of Marketing at CEVA.
  • "The availability of CEVA's Audio DSPs and software IP for the Intel Pathfinder for RISC-V program is another step in our commitment towards simplifying and accelerating the development of RISC-V platforms," said Vijay Krishnan, General Manager, RISC-V Ventures from Intel.
  • *Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries.

FLEX LOGIX AND CEVA ANNOUNCE FIRST WORKING SILICON OF A DSP WITH EMBEDDED FPGA TO ALLOW A FLEXIBLE/CHANGEABLE ISA

Retrieved on: 
Monday, June 27, 2022
Semiconductor, Image, FPGA, DSP, Industry, CEVA, IIA, ISA, Hillcrest Labs, Marketing, Communication, Software, Human, VP, Acceleration, ASIC, IOT, Efficiency, NB, AR, Ultra, IP, Solution, Sound, Architecture, UWB, Intelligence, Ecosystem, Interrupt, Robotics, Technology, Controller, GNSS, NASDAQ, AI, Silicon, VLIW, Luts, Original equipment manufacturer, TSMC, PC, IO, RAM, Bar-Ilan University, Algorithm, Video game console, Mobile phone, Bluetooth

MOUNTAIN VIEW, Calif., June 27, 2022 /PRNewswire/ -- Flex Logix® Technologies, Inc., the leading supplier of reconfigurable computing solutions, architecture and software, and CEVA, Inc. (NASDAQ: CEVA), the leading licensor of wireless connectivity and smart sensing technologies and integrated IP solutions, have announced today the world's first successful silicon implementation using Flex Logix's EFLX® embedded FPGA (eFPGA) connected to a CEVA-X2 DSP instruction extension interface. Enabling flexible and changeable instruction sets to meet demanding and changing processing workloads, the ASIC, known as SOC2, was designed and taped out in a TSMC 16 nm technology by Bar-Ilan University SoC Lab, as part of the HiPer Consortium, backed by the Israeli Innovation Authority (IIA).

Key Points: 
  • "The SOC2 contains two processing clusters, each containing two CEVA-X2 DSP cores and EFLX eFPGA for programming and executing DSP instructions extensions, connected using the CEVA-Xtend mechanism.
  • In addition to the ISA extension interface, EFLX has been used for packet processing, security, encryption, IO muxes, and general purpose algorithm acceleration.
  • CEVA-X2 supports various software needs using the extensive CEVA DSP Library, CEVA Neural Network Library, and a vast ecosystem partner offerings of software solutions for any application.
  • Flex Logix is headquartered in Mountain View, California and has offices in Austin, Texas and Vancouver, Canada.

CHELSIO WIDENS SMARTNIC LEADERSHIP WITH PIONEERING 7TH GENERATION UNIFIED WIRE

Retrieved on: 
Wednesday, April 27, 2022
Cloud, Cortex, GPU, Application-specific integrated circuit, InfiniBand, Family, CEO, VLIW, SSD, Software, Field-programmable gate array, Smart, PAM4, Architecture, Twitter, Workload, Movement, Arm, Silicon, ROI, HPC, OEM, RISC, Root complex, Security, Multimedia, DPU, View, ARM Cortex-A72, TSMC, CPU, PCI Express, FPGA, Snapshot (computer storage), RAID, Cloud computing, Video game console, Internet service provider, Cryptocurrency, Terminator, T5, T6, Chelsio Communications, Facebook

SUNNYVALE, Calif., April 27, 2022 /PRNewswire/ -- Chelsio Communications, Inc., a leading provider of high performance (1/2.5/10/25/40/50/100/200/400Gb) Ethernet Unified Wire Adapters and ASICs for storage networking, virtualized enterprise datacenters, cloud service installations, and cluster computing environments, today introduced its new 7th generation Unified Wire DPU product family architected to support and accelerate a wide range of networking, storage and security workloads supported by modern enterprise and cloud datacenter applications.

Key Points: 
  • It also integrates PCIe 5.0 x16 with the ability to be either Root Complex and/or End Point, a PCIe switch and an Ethernet switch.
  • T7 DPU supports all the host software of its predecessors, T5 & T6, as-is, thus enabling customers to leverage all prior software investment.
  • With T7 DPU, Chelsio also enters the computational storage market where on-the-fly compression and encryption increases the effective density of SSD drives.
  • The Chelsio Unified Wire DPU fully offloads all protocol traffic, providing no-compromise performance with high packet processing capacity, sub-microsecond hardware latency and high bandwidth.

ASPEED and CEVA Collaborate to Enable Superior Voice Experience on 2nd Generation Cupola360 SoC for Smart Cameras and Video Conferencing Systems

Retrieved on: 
Monday, January 3, 2022
Eclipse, NB, CEVA, 4-way, Real, Intelligent Platform Management Interface, IP, AGC, Monolithic kernel, RTOS, UWB, Forbes, AI, IOT, Hillcrest Labs, Marketing, Robotics, DSP, ISP, Broadcom Inc., BMC, Algorithm, NASDAQ, Solution, SIMD, Hyper, AFE, Ultra, Electronics, VLIW, SOC, ISA, LLVM, Organization, Original equipment manufacturer, Semiconductor, Videotelephony, MIC, Intelligence, AR, Interrupt, Human, Technology, Acquisition, PC, Image, Industry, Mobile phone, Video game console, Bluetooth

Chris Lin, Chairman and President of ASPEED Technology, commented: "Our 2nd generation Cupola360 SoC is our first product to incorporate real-time multi-image stitching video and powerful audio processing capabilities, making it perfect for video conferencing applications.

Key Points: 
  • Chris Lin, Chairman and President of ASPEED Technology, commented: "Our 2nd generation Cupola360 SoC is our first product to incorporate real-time multi-image stitching video and powerful audio processing capabilities, making it perfect for video conferencing applications.
  • Through the comprehensive cooperation between CEVA and ASPEED, our customers can enjoy the most superior video & audio functionality and we are glad to have CEVA as our strong and trusted partner."
  • ASPEED's 2nd generation Cupola360 multi-image stitching video & audio SoC, AST1230, as well as the accompanying app, is specifically designed for high performance video conferencing applications.
  • With a focus on advanced smart cameras for spherical video conferencing applications, the AST1230 SoC features include a powerful image signal processor (ISP) and a smart layout processing engine.

Synopsys Advances Processor IP Leadership with New ARC DSP IP Solutions for Low-Power Embedded SoCs

Retrieved on: 
Monday, September 20, 2021
ECC, ISO, SOC, PPA, Lidar, IOS, ISA, Research, ISO 26262, Compliance, 8-bit computing, ARC, MIT, Solution, Morbilliform, VLIW, Processor, AI, VPX, Radar, Marketing, DSP, Family, EDA, IOT, Silicon, EECS, Socs, SIMD, ASIL, Architecture, SNPS, Safety, Deep learning, Calendar, Machine learning, Fourier, COO, Acceleration, Metawar, Nasdaq, Natural language processing, PVT, Industry, Computer data storage, Video game console

The broad Synopsys DesignWare IP portfolio includes logic libraries, embedded memories, IOs, PVT monitors, embedded test, analog IP, interface IP, security IP, embedded processors and subsystems.

Key Points: 
  • The broad Synopsys DesignWare IP portfolio includes logic libraries, embedded memories, IOs, PVT monitors, embedded test, analog IP, interface IP, security IP, embedded processors and subsystems.
  • To accelerate prototyping, software development and integration of IP into SoCs, the company's IP Accelerated initiative offers IP prototyping kits, IP software development kits and IP subsystems.
  • The Synopsys DesignWare ARC VPX2 and VPX3 DSP Processor IP is scheduled to be available to lead customers in calendar Q4 2021.
  • The Synopsys DesignWare ARC VPX2FS and VPX3FS Processor IP is scheduled to be available to lead customers in calendar Q1 2022.