Accellera Forms SystemVerilog Mixed-Signal Interface Types Working Group
ELK GROVE, Calif., Feb. 07, 2024 (GLOBE NEWSWIRE) -- Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, announced today the formation of the SystemVerilog Mixed-Signal Interface Types (SystemVerilog MSI) Working Group (WG).
- ELK GROVE, Calif., Feb. 07, 2024 (GLOBE NEWSWIRE) -- Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, announced today the formation of the SystemVerilog Mixed-Signal Interface Types (SystemVerilog MSI) Working Group (WG).
- The scope of the new working group is to document a SystemVerilog-compatible language extension to permit interconnect, conversion, and resolution among dissimilar net types in SystemVerilog, including bidirectional connections.
- For more information on the SystemVerilog MSI Working group, visit the working group page .
- If you are not already an Accellera member and are interested in joining to participate in the working group and the ongoing development of the standard, visit here .