Instruction set architecture

Global Silicon Photonics Market (2020 to 2026) - Growing Potential of AI-Based Tools for Elderly Care Presents Opportunities

Retrieved on: 
Monday, June 29, 2020
Central processing unit, Computer architecture, Digital technology, Computing, Microprocessor, Computer, Processor, Instruction set architecture

The major restraint for the market is the reluctance among medical practitioners to adopt AI-based technologies and lack of a skilled workforce.

Key Points: 
  • The major restraint for the market is the reluctance among medical practitioners to adopt AI-based technologies and lack of a skilled workforce.
  • An MPU contains all or most of the CPU functions and is the engine that goes into motion when the computer is on.
  • A microprocessor is specially designed to perform arithmetic and logic operations that use small number-holding areas called registers.
  • These operations are the result of a set of instructions that are part of the microprocessor design.

Andes to Presents Andes Custom Extensions to the RISC-V V5 CPU Core for Creating Highly Competitive True Wireless Stereo SoC Designs

Retrieved on: 
Wednesday, March 11, 2020
Computer architecture, Computers, Digital technology, Instruction set architectures, Microcontrollers, RISC-V, Microprocessors, Reduced instruction set computer, Central processing unit, Multi-core processor, Instruction set architecture, Soft microprocessor

The first will feature Advanced Engineer Tung Wei describing how using Andes Custom Extensions (ACE) with Andes RISC-V CPU cores can create a highly competitive SoC.

Key Points: 
  • The first will feature Advanced Engineer Tung Wei describing how using Andes Custom Extensions (ACE) with Andes RISC-V CPU cores can create a highly competitive SoC.
  • Andes RISC-V CPU and it flexibility will create a friendly platform of design SoCs.
  • Using ACE to add acceleration to our D25F RISC-V CPU core enables SoC designers to enhance performance and reduce power of their SoC design.
  • Join the Andes RISC-V CON Online webinar series to learn how easy it is to add custom instructions for your TWS design.

IAR Systems Updates RISC-V Development Tools With Support for RV32E and Atomic Operations

Retrieved on: 
Tuesday, December 3, 2019
Computer architecture, Computing, Computers, Instruction set architectures, IAR Systems, Uppsala, Microcontrollers, RISC-V, Reduced instruction set computer, Workbench, IAR, Instruction set architecture

UPPSALA, Sweden, Dec. 3, 2019 /PRNewswire/ -- IAR Systems, the future-proof supplier of software tools and services for embedded development, announces that a new version of the toolchain IAR Embedded Workbench for RISC-V is now available.

Key Points: 
  • UPPSALA, Sweden, Dec. 3, 2019 /PRNewswire/ -- IAR Systems, the future-proof supplier of software tools and services for embedded development, announces that a new version of the toolchain IAR Embedded Workbench for RISC-V is now available.
  • Version 1.20 adds support for the base instruction set RV32E and also the standard extension for Atomic operations (A).
  • The standard extension for Atomic operations (A) adds instructions that support atomic read, modify, and write actions to support synchronization between different HW processes that access the same memory.
  • In May 2019, IAR Systems released the first version of IAR Embedded Workbench for RISC-V.

IAR Systems Updates RISC-V Development Tools With Support for RV32E and Atomic Operations

Retrieved on: 
Tuesday, December 3, 2019
Computer architecture, Computing, Computers, Instruction set architectures, IAR Systems, Uppsala, Microcontrollers, RISC-V, Reduced instruction set computer, Workbench, IAR, Instruction set architecture

UPPSALA, Sweden, Dec. 3, 2019 /PRNewswire/ -- IAR Systems, the future-proof supplier of software tools and services for embedded development, announces that a new version of the toolchain IAR Embedded Workbench for RISC-V is now available.

Key Points: 
  • UPPSALA, Sweden, Dec. 3, 2019 /PRNewswire/ -- IAR Systems, the future-proof supplier of software tools and services for embedded development, announces that a new version of the toolchain IAR Embedded Workbench for RISC-V is now available.
  • Version 1.20 adds support for the base instruction set RV32E and also the standard extension for Atomic operations (A).
  • The standard extension for Atomic operations (A) adds instructions that support atomic read, modify, and write actions to support synchronization between different HW processes that access the same memory.
  • In May 2019, IAR Systems released the first version of IAR Embedded Workbench for RISC-V.

SiFive Announces SiFive Learn Initiative

Retrieved on: 
Monday, December 2, 2019
Digital technology, Computer architecture, Computing, SiFive, Microcontrollers, Instruction set architectures, RISC-V, Central processing unit, Reduced instruction set computer, Instruction set architecture, Sands, Amazon Web Services

The SiFive Learn Inventor board is available for pre-order at https://www.pimoroni.com/sifive , and first shipments expected in December 2019.

Key Points: 
  • The SiFive Learn Inventor board is available for pre-order at https://www.pimoroni.com/sifive , and first shipments expected in December 2019.
  • The SiFive Learn Inventor board will be shown at Amazon AWS re:Invent in Las Vegas, NV, Dec. 2nd 6th.
  • Please visit the SiFive kiosk at the Sands Expo, hall B, level 2, booth #2704.
  • SiFive is the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture.

Andes Records Rapid Growth of RISC-V Processors Licensing Agreements in the First Half of 2019

Retrieved on: 
Wednesday, August 7, 2019
Computer architecture, Instruction set architectures, RISC-V, Reduced instruction set computer, Instruction set architecture, Microprocessor, ARM architecture

In 2019, Andes launched more series of new RISC-V cores.

Key Points: 
  • In 2019, Andes launched more series of new RISC-V cores.
  • In addition, Andes new 32-bit D25F is a low-power, high-performance core with DSP instruction set that serves DSP applications without Linux.
  • In the first half of 2019, Andes launched the RISC-V FreeStart program offering its commercial-grade CPU N22 RISC-V core with no upfront license fee.
  • Andes has taken part in more than 30 industry events that promoting RISC-V technology around the world in the first half of 2019.

SiFive Enhances Silicon Hills Operations with Office in Austin, Texas

Retrieved on: 
Tuesday, June 18, 2019
Computer architecture, Computers, Computing, Fabless semiconductor companies, Instruction set architectures, SiFive, Microcontrollers, RISC-V, Central processing unit, Reduced instruction set computer, Instruction set architecture

SAN MATEO, Calif., June 18, 2019 /PRNewswire/ -- SiFive , Inc., the leading provider of commercial RISC-V processor IP and silicon solutions, announced today it has further expanded its existing presence in the Austin, Texas, "Silicon Hills" area with the opening of an office to support all aspects of SiFive's business operations.

Key Points: 
  • SAN MATEO, Calif., June 18, 2019 /PRNewswire/ -- SiFive , Inc., the leading provider of commercial RISC-V processor IP and silicon solutions, announced today it has further expanded its existing presence in the Austin, Texas, "Silicon Hills" area with the opening of an office to support all aspects of SiFive's business operations.
  • There are 14 employees at the SiFive office, located in Bee Cave, covering sales, field application engineering, product, and marketing functions.
  • SiFive also recently secured $65 million in Series D funding to continue to fuel the innovation and leadership shown by SiFive in the RISC-V ecosystem.
  • SiFive is the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture.