Reduced instruction set computer

The 2021 RISC-V Summit Will Demonstrate Adoptions and Technical Advances This December in San Francisco

Retrieved on: 
Wednesday, July 28, 2021
Semiconductor, Hardware, Electronic design automation, Technology, Software, Computer architecture, Instruction set architectures, Computers, Computing, Reduced instruction set computer, RISC-V, Acorn Computers, RISC-V International, Design Automation Conference (DAC), RISC-V INTERNATIONAL, DESIGN AUTOMATION CONFERENCE (DAC)

RISC-V International announced the 2021 RISC-V Summit that will bring together the open hardware community for three days of deep technical talks, industry updates, networking, and more.

Key Points: 
  • RISC-V International announced the 2021 RISC-V Summit that will bring together the open hardware community for three days of deep technical talks, industry updates, networking, and more.
  • The RISC-V Summit will be held at Moscone West in San Francisco from December 6-8, 2021, and will feature hybrid in-person and virtual activities to connect with a global audience.
  • Were excited to be able to offer attendees an even richer event experience to inspire their future designs with our partnership with RISC-V Summit.
  • Sponsorship opportunities for the 2021 RISC-V Summit will be offered at the Diamond, Platinum, Gold, Silver, Bronze, and Startup and University levels.

CAES Receives Contract from Vinnova to Advance High Performance RISC-V Space Computing

Retrieved on: 
Monday, July 19, 2021
Semiconductor, Security, Technology, Satellite, Aerospace, Manufacturing, Computer architecture, Microprocessors, Computing, 64-bit computers, Instruction set architectures, European Space Agency, Leon, SPARC, Radiation hardening, Reduced instruction set computer, RISC-V

The new NOEL-V fault-tolerant, 64-bit processor core is based on the open RISC-V instruction set architecture and builds upon CAES heritage with the SPARC/LEON architecture.

Key Points: 
  • The new NOEL-V fault-tolerant, 64-bit processor core is based on the open RISC-V instruction set architecture and builds upon CAES heritage with the SPARC/LEON architecture.
  • It marks the newest addition to CAES trusted fault tolerant space computing product portfolio.
  • We look forward to working with Vinnova and our project partners to enhance our RISC-V processor technology to meet our customers next generation space program needs, said Mike Kahn, President and CEO of CAES.
  • The results of this initiative with Vinnova will inform our future radiation-hardened NOEL-V microprocessor development in collaboration with the European Space Agency, said Sandi Habinc, General Manager of Gaisler Products, CAES.

MEDIA ALERT: Join John Min, Andes Director of FAE for his RISC-V Forum Presentation “RISC-V Grows Up and Goes Big!”

Retrieved on: 
Monday, July 19, 2021
Computer architecture, Computing, Instruction set architectures, Technology, Microcontrollers, RISC-V, Reduced instruction set computer, Microprocessor

It will also describe RISC-V embedded technologies in the automotive industry, medical equipment, communications, graphic cards, and in disk drives.

Key Points: 
  • It will also describe RISC-V embedded technologies in the automotive industry, medical equipment, communications, graphic cards, and in disk drives.
  • Who: John Min, Andes Technology Corp.'s Director of FAE and specialist in Microprocessor based SOCs.
  • Why: John Mins presentation will detail the phenomenal growth for the RISC-V architecture over last 6 years.
  • Initially developed for academic research as a controller for Vector engine, it has found home in many embedded microcontrollers.

Canaan Releases Self-developed Edge AI Chip, the Kendryte K510

Retrieved on: 
Thursday, July 8, 2021
Computer architecture, Instruction set architectures, Reduced instruction set computer, RISC-V, Computing, Computers

BEIJING, July8 2021 /PRNewswire/ -- Canaan Inc. (NASDAQ: CAN) ("Canaan" or the "Company"), a leading high-performance computing solutions provider, today announced the release of the Kendryte K510 (the "K510"), an independently designed and developed RISC-V based edge AI chip, at the 2021 World Artificial Intelligence Conference.

Key Points: 
  • BEIJING, July8 2021 /PRNewswire/ -- Canaan Inc. (NASDAQ: CAN) ("Canaan" or the "Company"), a leading high-performance computing solutions provider, today announced the release of the Kendryte K510 (the "K510"), an independently designed and developed RISC-V based edge AI chip, at the 2021 World Artificial Intelligence Conference.
  • In addition, by adopting a RISC-V open-source architecture, the K510 is highly customizable and capable of empowering developers in their execution of scenario-based development.
  • Mr. Nangeng Zhang, Chairman and Chief Executive Officer of Canaan, commented, "The Kendryte K510 chip is the result of two years of work by our R&D team to further innovative and optimize our core chip architecture.
  • With upgraded machine vision and improved programming flexibility, the Kendryte K510 can better address the demands of mid- to high-end application scenarios.

Andes Technology Announces over 2 Billion Shipments of Andes-Embedded SoCs in 2020

Retrieved on: 
Tuesday, July 6, 2021
Computer architecture, Instruction set architectures, Microcontrollers, Andes Technology, Computing, RISC-V, Computers, Reduced instruction set computer, Symposium on Combinatorial Search, Fabless semiconductor companies

Although the pandemic has impacted the global economy, the SoC shipments containing Andes CPU IPs still hit a record high.

Key Points: 
  • Although the pandemic has impacted the global economy, the SoC shipments containing Andes CPU IPs still hit a record high.
  • Most of the 2 billion shipments in 2020 are Andes processors of the third generation architecture (V3), but Andes RISC-V series IPs launched in 2017 have started to contribute royalties as well, said Frankwell Lin, CEO of Andes Technology.
  • The production quantity of SoCs embedded with Andes processors reaches nearly 5.5 million units per day.
  • The annual volume of Andes-Embedded SoCs has exceeded 2 billion since 2020 and the cumulative volume has reached 7 billion.

IAR Systems extends development tools performance capabilities for Andes RISC-V cores

Retrieved on: 
Wednesday, June 23, 2021
Computer architecture, Computing, Computer engineering, IAR Systems, Uppsala, Microcontrollers, RISC-V, mbed, Reduced instruction set computer, IAR

Latest version of IAR Embedded Workbench for RISC-V adds support for latest Andes RISC-V processor technology, including AndeStar V5 RISC-V Performance Extension

Key Points: 
  • Latest version of IAR Embedded Workbench for RISC-V adds support for latest Andes RISC-V processor technology, including AndeStar V5 RISC-V Performance Extension
    UPPSALA, Sweden, June 23, 2021 /PRNewswire/ -- IAR Systems, the future-proof supplier of software tools and services for embedded development, presented a new version of its professional development tools for RISC-V. With the latest release, the complete development toolchain IAR Embedded Workbench for RISC-V adds support for latest Andes RISC-V extension and devices, enabling maximized performance in RISC-V-based applications.
  • With the support of the AndeStar V5 RISC-V Performance Extension, developers can use IAR Embedded Workbench to create applications with increased performance and reduced code size.
  • The toolchain supports all Andes 32-bit V5 RISC-V cores, including the N22, N25F, D25F, A25, A27, N45, D45 and A45.
  • Editor's Note: IAR Systems, IAR Embedded Workbench, Embedded Trust, C-Trust, C-SPY, C-RUN, C-STAT, IAR Visual State, IAR KickStart Kit, I-jet, I-jet Trace, I-scope, IAR Academy, IAR, and the logotype of IAR Systems are trademarks or registered trademarks owned by IAR Systems AB.

IAR Systems extends development tools performance capabilities for Andes RISC-V cores

Retrieved on: 
Wednesday, June 23, 2021
Computer architecture, Computing, Computer engineering, IAR Systems, Uppsala, Microcontrollers, RISC-V, mbed, Reduced instruction set computer, IAR

UPPSALA, Sweden, June 23, 2021 /PRNewswire/ -- IAR Systems, the future-proof supplier of software tools and services for embedded development, presented a new version of its professional development tools for RISC-V. With the latest release, the complete development toolchain IAR Embedded Workbench for RISC-V adds support for latest Andes RISC-V extension and devices, enabling maximized performance in RISC-V-based applications.

Key Points: 
  • UPPSALA, Sweden, June 23, 2021 /PRNewswire/ -- IAR Systems, the future-proof supplier of software tools and services for embedded development, presented a new version of its professional development tools for RISC-V. With the latest release, the complete development toolchain IAR Embedded Workbench for RISC-V adds support for latest Andes RISC-V extension and devices, enabling maximized performance in RISC-V-based applications.
  • With the support of the AndeStar V5 RISC-V Performance Extension, developers can use IAR Embedded Workbench to create applications with increased performance and reduced code size.
  • The toolchain supports all Andes 32-bit V5 RISC-V cores, including the N22, N25F, D25F, A25, A27, N45, D45 and A45.
  • Editor's Note: IAR Systems, IAR Embedded Workbench, Embedded Trust, C-Trust, C-SPY, C-RUN, C-STAT, IAR Visual State, IAR KickStart Kit, I-jet, I-jet Trace, I-scope, IAR Academy, IAR, and the logotype of IAR Systems are trademarks or registered trademarks owned by IAR Systems AB.

SiFive Performance P550 Core Sets New Standard as Highest Performance RISC-V Processor IP

Retrieved on: 
Tuesday, June 22, 2021
Software, Networks, Hardware, Electronic design automation, Technology, Semiconductor, Mobile, Wireless, Other Technology, Fabless semiconductor companies, Computer architecture, SiFive, Computing, Microcontrollers, 64-bit computers, Instruction set architectures, Computers, RISC-V, Reduced instruction set computer

SiFive, Inc., the industry leader in RISC-V processors and silicon solutions, today launched the new SiFive Performance family of processors.

Key Points: 
  • SiFive, Inc., the industry leader in RISC-V processors and silicon solutions, today launched the new SiFive Performance family of processors.
  • The SiFive Performance family debuts with two new processor cores, the P270, SiFives first Linux capable processor with full support for the RISC-V vector extension v1.0 rc, and the SiFive Performance P550 core, SiFives highest performance processor to date.
  • The new SiFive Performance P550 delivers a SPECInt 2006 score of 8.65/GHz, making it the highest performance RISC-V processor available today, and comparable to existing proprietary solutions in the application processor space.
  • Growing from its initial success in embedded processors to tackle the application processor market requires the performance, efficiency, and features demonstrated in the new SiFive Performance P550 core, said Kevin Krewell, Principal Analyst, TIRIAS Research.

StarFive Adopts Valtrix STING for Verification of Next-generation RISC-V Processors

Retrieved on: 
Tuesday, June 22, 2021
Computing, Computer engineering, Technology, Instruction set architectures, Microcontrollers, RISC-V, Reduced instruction set computer, System on a chip, Verification, E, Functional verification

BANGALORE, India, June 22, 2021 /PRNewswire/ -- Valtrix Systems , provider of design verification products for building functionally correct CPU and system-on-chip implementations, announced today that StarFive , a leading provider of RISC-V processors, platforms and solutions in China, has licensed STING for verification of the next generation of RISC-V processors.

Key Points: 
  • BANGALORE, India, June 22, 2021 /PRNewswire/ -- Valtrix Systems , provider of design verification products for building functionally correct CPU and system-on-chip implementations, announced today that StarFive , a leading provider of RISC-V processors, platforms and solutions in China, has licensed STING for verification of the next generation of RISC-V processors.
  • STING, a design verification product from Valtrix, uses software-driven methodology to check the functional correctness and architectural compliance of RISC-V implementations.
  • Its design verification tool STING features a highly flexible stimulus development framework and a large library of test stimulus.
  • For more information on Valtrix's design verification technology and products, visit: https://www.valtrix.in
    STING, the flagship product of Valtrix, is a commerically supported design verification tool for RISC-V based implementations.

StarFive Adopts Valtrix STING for Verification of Next-generation RISC-V Processors

Retrieved on: 
Tuesday, June 22, 2021
Computing, Computer engineering, Technology, Instruction set architectures, Microcontrollers, RISC-V, Reduced instruction set computer, System on a chip, Verification, E, Functional verification

BANGALORE, India, June 22, 2021 /PRNewswire/ -- Valtrix Systems , provider of design verification products for building functionally correct CPU and system-on-chip implementations, announced today that StarFive , a leading provider of RISC-V processors, platforms and solutions in China, has licensed STING for verification of the next generation of RISC-V processors.

Key Points: 
  • BANGALORE, India, June 22, 2021 /PRNewswire/ -- Valtrix Systems , provider of design verification products for building functionally correct CPU and system-on-chip implementations, announced today that StarFive , a leading provider of RISC-V processors, platforms and solutions in China, has licensed STING for verification of the next generation of RISC-V processors.
  • STING, a design verification product from Valtrix, uses software-driven methodology to check the functional correctness and architectural compliance of RISC-V implementations.
  • Its design verification tool STING features a highly flexible stimulus development framework and a large library of test stimulus.
  • For more information on Valtrix's design verification technology and products, visit: https://www.valtrix.in
    STING, the flagship product of Valtrix, is a commerically supported design verification tool for RISC-V based implementations.