MIPI Alliance

Mixel, Rambus and Hardent Collaborate to Deliver State-of-the-Art Integrated MIPI Display Subsystem Solution

Retrieved on: 
Wednesday, March 10, 2021
Fabless semiconductor companies, Rambus, MIPI Alliance

"We are excited to announce the combined solution with our Mixel MIPI Central partners, Rambus and Hardent, to fill a gap in the MIPI ecosystem," said Justin Endo, marketing manager at Mixel.

Key Points: 
  • "We are excited to announce the combined solution with our Mixel MIPI Central partners, Rambus and Hardent, to fill a gap in the MIPI ecosystem," said Justin Endo, marketing manager at Mixel.
  • "We are very pleased to launch this new display IP subsystem with our partners Mixel and Rambus," says Alain Legault, VP of IP products at Hardent.
  • For more information about the Mixel, Rambus and Hardent IP subsystem, register now to attend the webinar, " Next-Generation Displays: An Integrated IP Solution from Mixel, Rambus and Hardent "presented by the three companies on April 7th at 11:00am Pacific Time.
  • The Mixel, Rambus, and Hardent MIPI DSI-2 / VESA DSC subsystem solution is available today in both host (TX) and peripheral (RX) versions.

Arasan announces the immediate availability of its MIPI C-PHY / D-PHY Combo IP for SoC Designs on TSMC 22nm Process

Retrieved on: 
Monday, March 1, 2021
Integrated circuits, MIPI Alliance, PHY, TSMC, Telecommunications, Computing, Standards, Draft:Mixel, Camera Serial Interface

The MIPI C-PHY / D-PHY Combo IP is seamlessly integrated with Arasan own CSI Tx, CSI Rx, DSI Tx and DSI Rx as part of its Total MIPI Imaging and Display IP Solution.

Key Points: 
  • The MIPI C-PHY / D-PHY Combo IP is seamlessly integrated with Arasan own CSI Tx, CSI Rx, DSI Tx and DSI Rx as part of its Total MIPI Imaging and Display IP Solution.
  • Arasan's C-PHY / D-PHY IP is available for both TSMC 22nm ultra-low leakage (22ULL) and 22nm ultra-low power (22ULP)processes.
  • Arasan has been a contributing member to the MIPI Association 2005 with over a billion chips shipped with our MIPI IP.
  • Our MIPI CSI, DSI, D-PHY IP and C-PHY IP are also used in compliance and production testers further attesting the quality and compliance of Arasan IP.

Arasan announces the immediate availability of its MIPI C-PHY / D-PHY Combo IP for SoC Designs on TSMC 22nm Process

Retrieved on: 
Monday, March 1, 2021
Integrated circuits, MIPI Alliance, PHY, TSMC, Telecommunications, Computing, Standards, Draft:Mixel, Camera Serial Interface

The MIPI C-PHY / D-PHY Combo IP is seamlessly integrated with Arasan own CSI Tx, CSI Rx, DSI Tx and DSI Rx as part of its Total MIPI Imaging and Display IP Solution.

Key Points: 
  • The MIPI C-PHY / D-PHY Combo IP is seamlessly integrated with Arasan own CSI Tx, CSI Rx, DSI Tx and DSI Rx as part of its Total MIPI Imaging and Display IP Solution.
  • Arasan's C-PHY / D-PHY IP is available for both TSMC 22nm ultra-low leakage (22ULL) and 22nm ultra-low power (22ULP)processes.
  • Arasan has been a contributing member to the MIPI Association 2005 with over a billion chips shipped with our MIPI IP.
  • Our MIPI CSI, DSI, D-PHY IP and C-PHY IP are also used in compliance and production testers further attesting the quality and compliance of Arasan IP.

Industry's First MIPI M-PHY® GEAR 5 UFS 4.0 Protocol Analyzer and Exerciser

Retrieved on: 
Tuesday, February 16, 2021
Computing, Telecommunications, Standards, Embedded systems, Network protocols, UniPro, Universal Flash Storage, MIPI Alliance, M-PHY, PHY, Camera Serial Interface

These requirements are met with the high-speed MIPI M-PHY v5.0 Gear 5 (HS-G5) and JEDEC UFS 4.0 specification.

Key Points: 
  • These requirements are met with the high-speed MIPI M-PHY v5.0 Gear 5 (HS-G5) and JEDEC UFS 4.0 specification.
  • Trace Validation provides a complex analysis of link traffic such as UFS packet latency or UniPro Link Startup Sequences.
  • The Eclipse M52 UFS protocol analyzer/exerciser supporting UFS 3.1, UniPro v1.8 and M-PHY v4.1 is available for orders now.
  • MIPI, MIPI M-PHY and MIPI UniPro are registered trademarks owned by MIPI Alliance.

Faraday Unveils Complete Imaging and Display High-Speed Interface IP Set on UMC 28nm and 40nm Processes

Retrieved on: 
Thursday, January 21, 2021
Photography, Audio, Video, Hardware, Automotive, Technology, General Automotive, Other Technology, Security, Hardware acceleration, Integrated circuits, Computer buses, Computer engineering, MIPI Alliance, Low-voltage differential signaling, Application-specific integrated circuit, Computing, Technology

Faraday Technology Corporation (TWSE: 3035), a leading ASIC design service and IP provider, today unveiled its complete imaging and display high-speed interface IP set on UMCs 40LP and 28HPC/HPC+ process nodes, including MIPI D-PHY (TX/RX, controller), V-by-One HS (TX/RX, controller), and LVDS (TX/RX, I/O).

Key Points: 
  • Faraday Technology Corporation (TWSE: 3035), a leading ASIC design service and IP provider, today unveiled its complete imaging and display high-speed interface IP set on UMCs 40LP and 28HPC/HPC+ process nodes, including MIPI D-PHY (TX/RX, controller), V-by-One HS (TX/RX, controller), and LVDS (TX/RX, I/O).
  • Our comprehensive imaging and display interface IP solutions have successively been adopted for state-of-the-art applications at UMC 28nm and 40nm nodes, said Flash Lin, chief operating officer of Faraday.
  • By combining our proven records of imaging and display ASIC design experience, we can help our customers develop more high-performance systems with high-quality benefits to address the growing demand for imaging and display applications.
  • Faraday Technology Corporation (TWSE: 3035) is a leading ASIC design service and IP provider, certificated to ISO 9001 and ISO 26262.

Kopin’s 2.6K x 2.6K OLED Display Incorporated in Panasonic’s New VR Glasses

Retrieved on: 
Friday, January 15, 2021
Hardware, Audio, Video, Consumer electronics, Other Technology, Technology, Computer peripherals, Technology, Science and technology, Components, Eyewear, Emerging technologies, Display technology, Virtual reality headset, Glasses, Headset, OLED, MIPI Alliance, Kopin, Panasonic Corporation, 3M

This industry-leading 2.6K x 2.6K OLED microdisplay on Si integrates many functional blocks including MIPI serial interface, display stream compression (DSC) and memory.

Key Points: 
  • This industry-leading 2.6K x 2.6K OLED microdisplay on Si integrates many functional blocks including MIPI serial interface, display stream compression (DSC) and memory.
  • The Panasonic VR Glasses are the worlds first high-dynamic-range (HDR) capable, ultra-high-definition VR eyeglasses and offer stunning lifelike images.
  • The Panasonic VR Glasses has a very small form-factor thanks to the 1.3 displays and the slim Pancake optics.
  • The small, lightweight form factor makes the glasses comfortable to wear for extended periods of time, unlike todays bulky VR headsets.

Arasan Announces the Immediate Availability of its 2nd Generation MIPI D-PHY v1.1 IP for TSMC 22nm Process Technology

Retrieved on: 
Thursday, January 14, 2021
Digital electronics, MIPI Alliance, Electronic engineering, TSMC, Technology, Semiconductor intellectual property core, 7 nm process, 14 nm process, Draft:Mixel, MIPI Debug Architecture

The MIPI D-PHY IP is seamlessly integrated with Arasan's own DSI Tx and DSI Rx IP Cores as part of its Total MIPI Display IP Solution for wearables and IoT.

Key Points: 
  • The MIPI D-PHY IP is seamlessly integrated with Arasan's own DSI Tx and DSI Rx IP Cores as part of its Total MIPI Display IP Solution for wearables and IoT.
  • Arasan's D-PHY IP is available on both TSMC's industry-leading 22nm ultra-low power (22ULP) and 22nm ultra-low leakage (22ULL) process technologies.
  • Arasan has been a contributing member to the MIPI Association 2005 with over a billion chips shipped with its MIPI IP.
  • The MIPI D-PHY IP is also available off the shelf on the TSMC 40nm, 28nm, 16nm and 12nm process technologies.

Arasan Announces the Immediate Availability of its 2nd Generation MIPI D-PHY v1.1 IP for TSMC 22nm Process Technology

Retrieved on: 
Thursday, January 14, 2021
Digital electronics, MIPI Alliance, Electronic engineering, TSMC, Technology, Semiconductor intellectual property core, 7 nm process, 14 nm process, Draft:Mixel, MIPI Debug Architecture

The MIPI D-PHY IP is seamlessly integrated with Arasan's own DSI Tx and DSI Rx IP Cores as part of its Total MIPI Display IP Solution for wearables and IoT.

Key Points: 
  • The MIPI D-PHY IP is seamlessly integrated with Arasan's own DSI Tx and DSI Rx IP Cores as part of its Total MIPI Display IP Solution for wearables and IoT.
  • Arasan's D-PHY IP is available on both TSMC's industry-leading 22nm ultra-low power (22ULP) and 22nm ultra-low leakage (22ULL) process technologies.
  • Arasan has been a contributing member to the MIPI Association 2005 with over a billion chips shipped with its MIPI IP.
  • The MIPI D-PHY IP is also available off the shelf on the TSMC 40nm, 28nm, 16nm and 12nm process technologies.

Sofics and Hardent Join Mixel’s MIPI® Ecosystem to Provide Designers a Complete MIPI Solution

Retrieved on: 
Tuesday, December 15, 2020
Technology, Mobile, Wireless, Engineering, Audio, Video, Manufacturing, Other Technology, Telecommunications, Networks, Internet, Hardware, Electronic design automation, Semiconductor, Data management, Consumer electronics, MIPI Alliance, Telecommunications, M-PHY, Mixels, Computing, MIPI Debug Architecture, Mixel, Sofics, Hardent, MIPI Alliance

Sofics and Hardent are the newest members of the Mixel MIPI ecosystem known as Mixel MIPI Central and each companys IP will bring new product offerings to Mixel MIPI IP customers.

Key Points: 
  • Sofics and Hardent are the newest members of the Mixel MIPI ecosystem known as Mixel MIPI Central and each companys IP will bring new product offerings to Mixel MIPI IP customers.
  • Mixels MIPI PHY supports multiple standards, including MIPI D-PHYSM, MIPI C-PHYSM, and M-PHY, as well as dual-mode PHYs such as MIPI C-PHY/MIPI D-PHY combo and LVDS/MIPI D-PHY combo.
  • Together with Mixels MIPI PHY IP, Sofics provides a complete and best-in-class MIPI solution protected with low-leakage ESD solutions in a small footprint.
  • Combined with the existing MIPI Central members product portfolio, Sofics and Hardent round out the Mixel MIPI ecosystem with a more complete offering to customers interested in acquiring MIPI IP from Mixel.

Mixel MIPI D-PHY IP Integrated Into Hercules Microelectronics Award-Winning FPGA/Processor

Retrieved on: 
Tuesday, October 27, 2020
Semiconductor, Consumer electronics, Technology, Mobile, Wireless, Audio, Video, Hardware, Mixel, Hercules Microelectronics, MIPI Alliance

Mixel , a leading provider of mixed-signal intellectual property (IP), and Hercules Microelectronics (HME), a China-based developer of programmable FPGA cores, announced today that Mixels MIPI IP solution has been successfully integrated into HME-H1D03 FPGA and is in mass production.

Key Points: 
  • Mixel , a leading provider of mixed-signal intellectual property (IP), and Hercules Microelectronics (HME), a China-based developer of programmable FPGA cores, announced today that Mixels MIPI IP solution has been successfully integrated into HME-H1D03 FPGA and is in mass production.
  • Mixel provided Hercules Microelectronics with Mixels MIPI D-PHYSM Universal IP and HME achieved first-time silicon success.
  • The complete MIPI solution included three IP products delivered fully integrated and validated: Mixels MIPI D-PHY Universal IP, which can operate as either a transmitter or receiver, and the corresponding MIPI DSISM Host and Peripheral Controller Cores.
  • Mixel and the Mixel logo are registered trademarks of Mixel, Inc.
    MIPI and MIPI M-PHY are registered trademarks owned by MIPI Alliance.