Static timing analysis

Lattice Enhances Radiant Design Software with Expanded Functional Safety Capabilities

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星期一, 三月 25, 2024
Software, Networks, Internet, Hardware, Electronic Design Automation, Data Management, Technology, Semiconductor, Product marketing, Radiant, Synopsys, Lattice Semiconductor, IEC 61508, TMR, LSCC, System, IEC, I'm Upset, Marketing, Static timing analysis, Soft error, Lattice, Safety, DO-254, ISO, ISO 26262, Engineering, FPGA, Corporation, Sintering

Lattice Semiconductor (NASDAQ: LSCC), the low power programmable leader, today announced the latest release of its award-winning Lattice Radiant® design software, featuring expanded functional safety and reliability capabilities.

Key Points: 
  • Lattice Semiconductor (NASDAQ: LSCC), the low power programmable leader, today announced the latest release of its award-winning Lattice Radiant® design software, featuring expanded functional safety and reliability capabilities.
  • Now featuring integration with the latest Synopsys Synplify® FPGA synthesis tool with TMR, Lattice Radiant offers an advanced design automation flow solution that enables designers to more easily develop Lattice FPGA-based applications with the robust functional safety protections, high reliability, and dependable operation required for the Industrial, Automotive, and Avionics markets.
  • Establishing protocols for functional safety and error mitigation compliant with industry standards, namely DO-254, IEC 61508, and ISO 26262, is integral to developing and validating highly reliable and safety-critical designs.
  • “The latest Radiant software with Synopsys TMR capabilities will provide automated synthesis protocol with enhanced efficiency and reliability, enabling designers to further explore the robustness of our low power, small form factor FPGAs.”
    The latest Lattice Radiant release includes:
    Safety Critical Block-Based Design Flow.

Monozukuri’s GENIO™ Co-Design EDA Tool Now Includes Parasitic Estimation and Stack Planning Functionality

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星期二, 一月 18, 2022
Hardware, Electronic Design Automation, Other Technology, Technology, Software, RC, Technology, TSV, EDA, TSV Amicitia Viernheim, Automation, Efficiency, Multimedia, 3D, Architecture, Static timing analysis, Video game console, 3D printing, Printed circuit board, Monozukuri

MZ Technologies, the marketing arm of Monozukuri s.P.a., today unveiled GENIO 1.6 that includes Parasitic Estimation and Stack Planning functionality to further slash total design time and reduces overall design complexity.

Key Points: 
  • MZ Technologies, the marketing arm of Monozukuri s.P.a., today unveiled GENIO 1.6 that includes Parasitic Estimation and Stack Planning functionality to further slash total design time and reduces overall design complexity.
  • Parasitic Estimation is implemented after a chiplet-based system design and its system-level interconnects have optimized end-to-end 3D-aware signal assignment.
  • The Stack Planning Support automatically identifies the best 3D stack configuration, given physical and electrical constraints.
  • Stack Planning provides a detailed comparison of multiple floor planning scenarios that allow the early comparison of multiple architecture configurations.

Synopsys, TSMC and Microsoft Azure Deliver Highly Scalable Timing Signoff Flow in the Cloud

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星期一, 六月 15, 2020
Digital technology, Cloud computing, Computing, Cloud infrastructure, Electronic design automation, Formal methods, Signoff, Static timing analysis, Synopsys, Parasitic extraction, Microsoft Azure

Significant throughput gains with PrimeTime timing signoff and StarRC extraction for multi-scenario, distributed processing runs

Key Points: 
  • Significant throughput gains with PrimeTime timing signoff and StarRC extraction for multi-scenario, distributed processing runs
    Synopsys, Inc. (Nasdaq:SNPS) today announced its collaboration with TSMC and Microsoft has delivered a ground-breaking, highly scalable timing signoff flow for use in the cloud.
  • The flow dramatically improves throughput using Synopsys PrimeTime static timing analysis and StarRC parasitic extraction on the Microsoft Azure platform.
  • TSMC is the first foundry to collaborate with design ecosystem partners and cloud providers to enable design in the cloud.
  • On a multi-million gate design using the TSMC N5 process, PrimeTime static timing analysis and StarRC extraction, timing signoff was performed on Microsoft Azure's latest Edsv4-series compute instances.