Verilog

GOWIN's progress in global automotive market gathers momentum with award of ISO 26262 certification for its FPGA design environment

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火曜日, 4月 30, 2024
ISO 14001, TSMC, VHDL, IP, TUV, Safety, LVDS, Certification, PCI Express, Verilog, IEC, ISO, ISO 9001, Original equipment manufacturer, MIPI, Environment, SystemVerilog, Field-programmable gate array, Memory, DDR3, Medical device

LONDON and GUANGZHOU, China, April 30, 2024 /PRNewswire/ -- GOWIN Semiconductor Corporation, the world's fastest-growing FPGA manufacturer, today announced that its GOWIN EDA FPGA design environment has been certified compliant with the ISO 26262 and IEC 61508 functional safety standards by the TUV testing laboratory.

Key Points: 
  • Certification of the FPGA design tool provides strong assurance to automotive OEMs that module designs featuring a GOWIN Arora-V (mid-density), Arora-II (low-/mid-density) or LittleBee (low-density) FPGA can meet the requirements for system-level functional safety specified in the ISO 26262 and IEC 61508 standards.
  • Existing quality and reliability certificates applicable to the GOWIN product range include IATF16949, ISO 9001, ISO 14001 and ISO/IEC 17025.
  • The GOWIN EDA FPGA design environment includes an FPGA design tool, IP cores and reference designs.
  • GOWIN's automotive-qualified FPGA product range and the GOWIN EDA development environment can be viewed at its stand 3A.340 at Embedded World (Nuremberg, Germany, 9-11 April 2024).

GOWIN's progress in global automotive market gathers momentum with award of ISO 26262 certification for its FPGA design environment

Retrieved on: 
火曜日, 4月 30, 2024
ISO 14001, TSMC, VHDL, IP, TUV, Safety, LVDS, Certification, PCI Express, Verilog, IEC, ISO, ISO 9001, Original equipment manufacturer, MIPI, Environment, SystemVerilog, Field-programmable gate array, Memory, DDR3, Medical device

LONDON and GUANGZHOU, China, April 30, 2024 /PRNewswire/ -- GOWIN Semiconductor Corporation, the world's fastest-growing FPGA manufacturer, today announced that its GOWIN EDA FPGA design environment has been certified compliant with the ISO 26262 and IEC 61508 functional safety standards by the TUV testing laboratory.

Key Points: 
  • Certification of the FPGA design tool provides strong assurance to automotive OEMs that module designs featuring a GOWIN Arora-V (mid-density), Arora-II (low-/mid-density) or LittleBee (low-density) FPGA can meet the requirements for system-level functional safety specified in the ISO 26262 and IEC 61508 standards.
  • Existing quality and reliability certificates applicable to the GOWIN product range include IATF16949, ISO 9001, ISO 14001 and ISO/IEC 17025.
  • The GOWIN EDA FPGA design environment includes an FPGA design tool, IP cores and reference designs.
  • GOWIN's automotive-qualified FPGA product range and the GOWIN EDA development environment can be viewed at its stand 3A.340 at Embedded World (Nuremberg, Germany, 9-11 April 2024).

Ansys and TSMC Enable a Multiphysics Platform for Optics and Photonics, Addressing Needs of AI, HPC Silicon Systems

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水曜日, 4月 24, 2024
Synopsys, Process, HPC, TSMC, Verilog, Silicon, OIP, Innovation, Communication, Artificial intelligence, Transport, PDK, Compiler, Process design kit, Silicon photonics, Electronics, TMI, ANSYS, Printed circuit board

PITTSBURGH, April 24, 2024 /PRNewswire/ -- Ansys (NASDAQ: ANSS) today announced a collaboration with TSMC on multiphysics software for TSMC's Compact Universal Photonic Engines (COUPE). COUPE is a cutting-edge Silicon Photonics (SiPh) integration system and Co-Packaged Optics platform that mitigates coupling loss while significantly accelerating chip-to-chip and machine-to-machine communication.

Key Points: 
  • COUPE is a cutting-edge Silicon Photonics (SiPh) integration system and Co-Packaged Optics platform that mitigates coupling loss while significantly accelerating chip-to-chip and machine-to-machine communication.
  • TSMC COUPE, along with Ansys multiphysics solutions that are integrated with Synopsys' 3DIC Compiler unified exploration-to-signoff platform, enables the next generation of silicon photonics and co-packaged optics designs for applications in AI, datacenter, cloud, and HPC communications.
  • The work spans multiple areas, including fiber-to-chip coupling, integrated electronic-photonic chip design, power integrity verification, high-frequency electromagnetic analysis, and critical thermal management.
  • TSMC COUPE integrates multiple electrical ICs with a photonic IC and fiber optic connections into a single package.

Accellera Systems Initiative Honors Shalom Bresticker with First Distinguished Service Award

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火曜日, 2月 27, 2024
Dai, ELK, OVL, Verilog, SystemVerilog, Electronics, Distinguished Service Award, Verilog-AMS, Princeton University, Documentation, EDA, Knowledge, IEEE, Lady Davis Fellows, Nursing

ELK GROVE, Calif., Feb. 27, 2024 (GLOBE NEWSWIRE) -- Accellera Systems Initiative (Accellera) announced today that Shalom Bresticker, a longtime friend and contributor to Accellera standards efforts, is honored with the first Distinguished Service Award.

Key Points: 
  • ELK GROVE, Calif., Feb. 27, 2024 (GLOBE NEWSWIRE) -- Accellera Systems Initiative (Accellera) announced today that Shalom Bresticker, a longtime friend and contributor to Accellera standards efforts, is honored with the first Distinguished Service Award.
  • Mr. Bresticker has been an electronics engineer for 30 years and more recently a technical editor for nearly a decade.
  • He was awarded the Accellera Technical Excellence Award in 2010 for his contributions to the Verilog, SystemVerilog, Verilog-AMS and OVL standards.
  • “Shalom has been an invaluable contributor to the development of Accellera standards,” stated Lu Dai, Accellera Chair.

INDUSTRY LEADING PPA DSP AVAILABLE FOR ALL EXISTING EFLX EFPGA

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水曜日, 3月 6, 2024
Compiler, Simulink, TPU, Verilog, Silicon, Macs, Complex, FFT, IP, DSP, FPGA

MOUNTAIN VIEW, Calif., March 6, 2024 /PRNewswire/ -- Flex Logix® Technologies, Inc., the leading supplier of embedded FPGA (eFPGA) IP and reconfigurable DSP/AI solutions, announced today that InferX DSP is in development for use with existing EFLX eFPGA from 40nm to 7nm.

Key Points: 
  • MOUNTAIN VIEW, Calif., March 6, 2024 /PRNewswire/ -- Flex Logix® Technologies, Inc. , the leading supplier of embedded FPGA (eFPGA) IP and reconfigurable DSP/AI solutions, announced today that InferX DSP is in development for use with existing EFLX eFPGA from 40nm to 7nm.
  • One, two, four, eight or 16 TPUs can be controlled by existing EFLX eFPGA from 40nm to 7nm.
  • "InferX with existing EFLX eFPGA allows us to deliver much higher DSP throughput at much lower cost than eFPGA with MACs.
  • Benchmarks are available for all of the process nodes we have silicon for now: 40, 28, 22, 16, 12, 7nm.

Industry Veterans Atiq Raza and Prabhu Goel Join minds.ai Board of Directors

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火曜日, 10月 24, 2023
CHIPS, 2020 North Macedonian parliamentary election, Gateway Design Automation, European Chips Act, AMD, Automation, Artificial intelligence, Learning, Growth, Verilog, Maestro, Deep learning, IBM, Management, Cryptocurrency

SANTA CRUZ, Calif., Oct. 24, 2023 /PRNewswire/ -- minds.ai announced today that Atiq Raza and Prabhu Goel have joined the board of directors, bringing decades of experience in the semiconductor industry to the company. Their expertise will help guide the company as it expands deployment of its minds.ai Maestro™ solution to optimize semiconductor production while slashing manufacturing cost and waste.

Key Points: 
  • SANTA CRUZ, Calif., Oct. 24, 2023 /PRNewswire/ -- minds.ai announced today that Atiq Raza and Prabhu Goel have joined the board of directors, bringing decades of experience in the semiconductor industry to the company.
  • Goel is a managing partner at Green Span Ventures and at Goel Family Ventures, which invest in enterprise software and renewable energy.
  • Atiq Raza, executive board chair, minds.ai, said: "The reason I leaned in at minds.ai is the impression made on me regarding the amazing talent of the team.
  • Prabhu Goel, board member, minds.ai, said: "As an active venture investor, I'm always looking for innovative ideas.

Efabless Launches 3rd AI-Generated Open-Source AI Contest to Extend the Caravel SoC Platform with AI-Generated Peripherals

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月曜日, 9月 25, 2023
Bard, RTL, ChatGPT, PALO, Boat, Caravel, Creativity, Documentation, GDS, Verilog, AI, Automation, Copper, Medical device

PALO ALTO, Calif., Sept. 25, 2023 (GLOBE NEWSWIRE) -- Efabless Corporation, the creator platform for chips, is excited to announce the launch of its 3rd AI-Generated Open-Source AI Contest.

Key Points: 
  • PALO ALTO, Calif., Sept. 25, 2023 (GLOBE NEWSWIRE) -- Efabless Corporation, the creator platform for chips, is excited to announce the launch of its 3rd AI-Generated Open-Source AI Contest.
  • This unique competition invites participants to utilize generative AI tools such as chatGPT, Bard, or similar, to generate open-source silicon designs.
  • The Efabless SoC platform is called “Caravel” – after the small but fast and maneuverable sailing ships built in Spain and Portugal starting in the 15th century.
  • The theme for this contest, “Float the Boat,” plays off of the platform name and focuses on extending the Caravel SoC with useful and verified AI-generated peripherals.

FLEX LOGIX ANNOUNCES RECONFIGURABLE BLOCK RAM WITH ECC OPTION

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月曜日, 9月 18, 2023
ECC, Urinary tract infection, Reconfigurable computing, Correction, Parity, IP, Ticketmaster, LLC v. RMG Technologies, Inc., Computer data storage, Verilog

MOUNTAIN VIEW, Calif.,  Sept. 18, 2023 /PRNewswire/ --  Flex Logix® Technologies, Inc., the leading supplier of eFPGA IP, announced today the availability of Reconfigurable Block RAM with ECC and Parity Options.

Key Points: 
  • MOUNTAIN VIEW, Calif., Sept. 18, 2023 /PRNewswire/ -- Flex Logix® Technologies, Inc ., the leading supplier of eFPGA IP, announced today the availability of Reconfigurable Block RAM with ECC and Parity Options.
  • "Our customers want Block RAM (BRAM) that is flexible.
  • BRAM access can be configured for single port or two port or true dual port," said Geoff Tate, CEO of Flex Logix.
  • Now we have a single Reconfigurable Block RAM that can meet all of these needs."

Efabless Design Challenge Winners Advance the Power of AI in Chip Design

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水曜日, 9月 13, 2023
Crypto, Learning, RTL, Integrated circuit, Challenge, PALO, Synthetic media, ChatGPT, IC, SOC, Caravel, CNN, Convolutional neural network, Documentation, TensorFlow, Data, Generative, AI, First Ever, MNIST, Medical device, Verilog

PALO ALTO, Calif., Sept. 13, 2023 (GLOBE NEWSWIRE) -- Efabless Corporation, the creator platform for chips, today announced the first, second, and third-place winners of its Second AI Generated Open-Source Silicon Design Challenge.

Key Points: 
  • PALO ALTO, Calif., Sept. 13, 2023 (GLOBE NEWSWIRE) -- Efabless Corporation, the creator platform for chips, today announced the first, second, and third-place winners of its Second AI Generated Open-Source Silicon Design Challenge.
  • The AI Generated Open-Source Silicon Design Challenges are a part of Efabless’ initiative to democratize the use of Generative AI for chip design.
  • The initiative drives innovation and learning in the chip design community by:
    Advancing the capabilities of generative AI use for chip design and verification, as well as secure device implementation.
  • The Verilog designs are then implemented using the chipIgnite Caravel SoC template and an open-source design flow such as OpenLane.

Tachyum Offers Its TPU Inference IP to Edge and Embedded Markets

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火曜日, 9月 12, 2023
Semiconductor, Hardware, Data Management, Technology, Artificial Intelligence, RTL, TAI, Internet of things, IP, TPU, CAPEX, HPC, Experiential learning, Artificial intelligence, Prodigy, Architecture, OPEX, AI, Universal, Economics, GPU, Medical device, Verilog

Tachyum ® today announced that it is expanding the unique value proposition of its Tachyum Prodigy by offering its Tachyum TPU® (Tachyum Processing Unit) intellectual property as a licensable core, allowing developers to take full advantage of intelligent, datacenter-trained AI when making IoT and Edge devices.

Key Points: 
  • Tachyum ® today announced that it is expanding the unique value proposition of its Tachyum Prodigy by offering its Tachyum TPU® (Tachyum Processing Unit) intellectual property as a licensable core, allowing developers to take full advantage of intelligent, datacenter-trained AI when making IoT and Edge devices.
  • With the tremendous growth of the AI chipset market for edge inference, Tachyum is looking to extend its proprietary Tachyum AI data type beyond the datacenter by providing its internationally registered and trademarked IP to outside developers.
  • Key features of the TPU inference and generative AI/ML IP architecture include architectural transactional and cycle accurate simulators; tools and compilers support; and hardware licensable IP, including RTL in Verilog, UVM Testbench and synthesis constraints.
  • For licensing opportunities of Tachyum’s TPU IP, interested vendors are invited to contact the company at https://www.tachyum.com/contact/ .