Reliability verification

GBT received a noticed of publication for its Integrated Circuit’s Geometrical Design Rule Automatic Correction patent

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星期三, 十二月 21, 2022

Patent, Research, SAN, Artificial intelligence, OTC, Intellectual property, Silicon, Omega, Reliability verification, Video game console, 3D printing

SAN DIEGO, Dec. 21, 2022 (GLOBE NEWSWIRE) -- GBT Technologies Inc. (OTC PINK: GTCH) ("GBT” or the “Company”), received a notice of publication for its nonprovisional patent application for integrated circuits (“IC”) geometrical design rule automatic correction system and method, which has been assigned an internal code name Omega. The patent application was published on December 8, 2022 as U.S. Patent Application Publication No. 2022/0390831. The patent application seeks to protect the Company’s intellectual property for automatic correction of geometrical design rule violations within an IC’s layout. Typically, this type of correction is done manually and takes a considerable amount of time to perform. The goal of the intellectual property is to automatically correct the IC’s layout without manual intervention, maintaining its electrical connectivity and keeping compliance with design for manufacturing (“DFM”) and Reliability Verification (“RV”) constraints. Particularly, in advanced nanometer nodes of 7nm and below, a manual design rule correction may take a significant amount of time, and increase the overall project’s design time. The patent application describes a technology that can perform the correction within minutes using Artificial Intelligence neural networks algorithms. The patent application describes a capability to perform a full hierarchical correction throughout the microchip’s sub-blocks considering electrical and manufacturing aspects.

Key Points:

The patent application was published on December 8, 2022 as U.S. Patent Application Publication No.
The patent application seeks to protect the Company’s intellectual property for automatic correction of geometrical design rule violations within an IC’s layout.
Particularly, in advanced nanometer nodes of 7nm and below, a manual design rule correction may take a significant amount of time, and increase the overall project’s design time.
Geometrical design rules are constraints dictated by the fabrication process and must be obeyed to correctly manufacture an integrated circuit.

iST, the first Asia laboratory to join the Automotive Electronics Council (AEC) as an Associate Member

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星期四, 十一月 10, 2022

TAIPEI, Nov. 10, 2022 /PRNewswire/ --Integrated Service Technology Inc. (iST) announced today that after going through tedious multiple reviews, the Automotive Electronics Council (AEC) the highest level of global automotive electronics qualification association has recently officially recognized iST as one of its Associate Member.

Key Points:

TAIPEI, Nov. 10, 2022 /PRNewswire/ --Integrated Service Technology Inc. (iST) announced today that after going through tedious multiple reviews, the Automotive Electronics Council (AEC) the highest level of global automotive electronics qualification association has recently officially recognized iST as one of its Associate Member.
There are only 93 firms in the world, 9 firms from Taiwan, to have become an AEC member.
These 9 Taiwan firms include TSMC and UMC foundries, and iST is honored to be the only laboratory in Asia recognized as part of this international elite team.
There are only 93 qualified AEC members in the world and are all distinguished firms in their respective automobile fields.

GBT’s Automatic Correction of Integrated Circuits Connectivity Mismatches Non-Provisional Patent Application has been Approved for Prioritized Examination

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星期三, 九月 14, 2022

The patent application will undergo prioritized examination to accelerate the process.

Key Points:

The patent application will undergo prioritized examination to accelerate the process.
The original patent was filed on August 3, 2022 (application #17880055) to protect programmatic methodologies and algorithms to automate integrated circuits electrical connectivity mismatches correction, with the goal of shortening microchips design cycle, particularly for advanced nanometer nodes of 5nm and below.
Particularly with Analog or MIXED layout types, these mismatches would have to be fixed manually which is a tedious, time consuming, manual design work.
GBTs non-provisional patent application seeks to protect an algorithmic system and method to perform this process automatically.

GBT is Seeking to Develop its own Microchip’s Design Rule Standard Language and Format

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星期二, 八月 30, 2022

SAN DIEGO, Aug. 30, 2022 (GLOBE NEWSWIRE) -- GBT Technologies Inc. (OTC PINK: GTCH) ("GBT” or the “Company”), is developing its own Integrated Circuit (IC) Design Rule Description language and format with the goal of enabling a secured, proprietary rule deck to be used in all of its current and future Electric Design Automation (EDA) tools. The GBT EDA technology is targeted to read a microchip’s process manufacturing rules, understanding its geometrical, electrical and manufacturing featured dimensions and constraints. These rules, provided by the fabrication plant, are the reference for GBT’s computer programs to analyze the IC data. This process is called IC verification and it is done in few domains, which are geometrical (DRC - Design Rule Check), Connectivity (LVS - Layout vs Schematic), Reliability (RV – Reliability Verification) and DFM (Design for Manufacturing). In order to enable a mathematical language to describe these rules, GBT is developing its own standard rules language and format called GSR (GBT Standard Rules). This format is planned to be implemented using Python language due to its fast performance and flexibility. GBT’s EDA technologies, among them are Epsilon (For Reliability Verification) and Omega (Geometrical Design Rule Aware Environment) will be using the proprietary rule deck as an input. Fabrication plant design rule description will be converted into GSR (GBT’s Standard Rule) format and encrypted to ensure security and confidentiality. GBT’s rule file will be governing the microchip’s layers definition, mathematical/logic operations and manufacturing rules. Once developed, it is the goal that GBT’s proprietary new language and format will ensure rapid IC process rules understanding, processing and robust security. Particularly with advanced nodes of 5nm and below there is a need to ensure rapid understanding of complex geometrical, connectivity, electrical and manufacturing rules. The new language and format enable a comprehensive rule description to support analog, digital and mixed design styles. The new standard language is planned to be used in all future GBT EDA technologies.

Key Points:

In order to enable a mathematical language to describe these rules, GBT is developing its own standard rules language and format called GSR (GBT Standard Rules).
GBTs EDA technologies, among them are Epsilon (For Reliability Verification) and Omega (Geometrical Design Rule Aware Environment) will be using the proprietary rule deck as an input.
Fabrication plant design rule description will be converted into GSR (GBTs Standard Rule) format and encrypted to ensure security and confidentiality.
The new language and format enable a comprehensive rule description to support analog, digital and mixed design styles.

GBT Filed a Non-Provisional Patent Application Seeking to Protect the Automatic Correction of Integrated Circuits Connectivity Mismatches

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星期二, 八月 16, 2022

SAN DIEGO, Aug. 16, 2022 (GLOBE NEWSWIRE) -- GBT Technologies Inc. ( OTC PINK:GTCH ) ("GBT or the Company) filed a nonprovisional patent application for automatic correction of Integrated Circuits (IC) electrical connectivity mismatches system and method.

Key Points:

SAN DIEGO, Aug. 16, 2022 (GLOBE NEWSWIRE) -- GBT Technologies Inc. ( OTC PINK:GTCH ) ("GBT or the Company) filed a nonprovisional patent application for automatic correction of Integrated Circuits (IC) electrical connectivity mismatches system and method.
The nonprovisional patent application seeks to protects programmatic methodologies and algorithms to automate ICs electrical connectivity mismatches correction to achieve faster and more efficient designs, particularly for advanced nanometer range of 5nm and below.
GBTs nonprovisional patent application seeks to protect an algorithmic systems and method to perform an automatic LVS correction with a click of a button.
Our nonprovisional patent application seeks to protect an automated LVS correction system to analyze an entire chip data, checks for electrical connectivity mismatches and Auto-Corrects them with a click of a button.