CDNS

Cadence to Acquire Rambus PHY IP Assets

Retrieved on: 
Giovedì, Luglio 20, 2023
Software, Networks, Hardware, Electronic Design Automation, Artificial Intelligence, Data Management, Technology, Semiconductor, Cadence Design Systems, IP Group, PHY, CDNS, SerDes, Calendar, RMBS, IP, Rambus Inc. v. Nvidia, Acquisition, Rambus, CPU, Growth, AI, Silicon, Memory, Video game, Cadence

Cadence Design Systems, Inc. (Nasdaq: CDNS) and Rambus Inc. (Nasdaq: RMBS), a premier chip and silicon IP provider making data faster and safer, today announced that they have entered into a definitive agreement for Cadence to acquire the Rambus SerDes and memory interface PHY IP business.

Key Points: 
  • Cadence Design Systems, Inc. (Nasdaq: CDNS) and Rambus Inc. (Nasdaq: RMBS), a premier chip and silicon IP provider making data faster and safer, today announced that they have entered into a definitive agreement for Cadence to acquire the Rambus SerDes and memory interface PHY IP business.
  • Rambus will retain its digital IP business, including memory and interface controllers and security IP.
  • The expected technology asset purchase also brings Cadence proven and experienced PHY engineering teams in the United States, India and Canada, further expanding Cadence’s domain-rich talent base.
  • View the full release here: https://www.businesswire.com/news/home/20230720477858/en/
    “Memory and SerDes IP design and integration continues to be integral to the design of AI, data center and hyperscale applications, CPU architectures and networking devices, and the addition of the Rambus IP and seasoned team further accelerates Cadence’s Intelligent System Design strategy, which drives design excellence,” said Boyd Phelps, senior vice president and general manager of the IP Group at Cadence.

Cadence, GlobalFoundries, Hoerzentrum Oldenburg and Leibniz University Hannover Collaborate to Advance Hearing Aid Technology

Retrieved on: 
Martedì, Luglio 18, 2023
Software, Hardware, General Health, Health, Electronic Design Automation, Medical Devices, Technology, Semiconductor, Cadence Design Systems, IP Group, Life, CDNS, Hearing, DSP, GlobalFoundries, German, Smart, ABB, Research, Leibniz University Hannover, SOC, Federal Ministry of Petroleum Resources (Nigeria), Hearing aid, Intelligent system, MBH, VDD, Algorithm, IMS, Kool-Aid, Education, Longevity, PPA, GF, Automation, 3D printing, Medical device, Cassette tape, Cadence

The SmartHeAP SoC prototype provides hearing aid companies with all the components required to create and reprogram hearing devices that improve a wearer’s hearing experience.

Key Points: 
  • The SmartHeAP SoC prototype provides hearing aid companies with all the components required to create and reprogram hearing devices that improve a wearer’s hearing experience.
  • Cost Savings: The hearing aid software can be quickly upgraded without replacing the hardware, saving both the wearers and the hearing aid companies money.
  • “The collaboration between GF, Cadence, Hoerzentrum Oldenburg gGmbH and Leibniz University Hannover resulted in a successful hearing aid SoC that consumes significantly less power while providing hearing aid wearers with the first-of-its-kind binaural technology that transforms how they process a complete auditory scene.
  • By collaborating with Cadence, GF and Hoerzentrum Oldenburg gGmbH, we’re bringing the joy of hearing back to hearing aid wearers with this new SoC prototype.”

Cadence Unveils Joules RTL Design Studio, Delivering Breakthrough Gains in RTL Productivity and Quality of Results

Retrieved on: 
Venerdì, Luglio 14, 2023
Software, Data Analytics, Hardware, Electronic Design Automation, Artificial Intelligence, Professional Services, Technology, Semiconductor, Congestion, Cadence Design Systems, RTL, CDNS, QOR, Intelligence, Multimedia, SOC, Silicon, Joule, GUI, Intelligent system, Socs, AI, Digital, PPAC, MediaTek, PPA, Unified, Industrial and production engineering, Video game, Risk management, Cadence, IP

Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the delivery of the Cadence® Joules™ RTL Design Studio, a new solution that provides users with actionable intelligence to accelerate the register transfer level (RTL) design and implementation process.

Key Points: 
  • Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the delivery of the Cadence® Joules™ RTL Design Studio, a new solution that provides users with actionable intelligence to accelerate the register transfer level (RTL) design and implementation process.
  • With Joules RTL Design Studio, users can achieve physical estimates quickly and accurately, unlocking up to 5X productivity and up to 25% quality of results (QoR) improvements in the RTL.
  • View the full release here: https://www.businesswire.com/news/home/20230713175152/en/
    The new Cadence Joules RTL Design Studio provides users with actionable intelligence to accelerate the register transfer level (RTL) design and implementation process, delivering up to 5X faster RTL convergence and up to 25% improved QoR.
  • Now, by leveraging Joules RTL Design Studio from Cadence, we can achieve efficient and accurate power breakdown analysis much earlier in the design phase.

Cadence Digital, Custom/Analog Design Flows Certified and Design IP Available for Intel 16 FinFET Process

Retrieved on: 
Martedì, Luglio 11, 2023
Data Management, Technology, Other Technology, Software, Internet, Hardware, Database, DRC, Kurdistan, MIPI, Cadence Design Systems, PCI Express, PHY, CDNS, USB 3.2, EDA, Virtuoso, WSP, USB, Intel, IP, SOC, Government, Proposed UK Internet age verification system, PCI, Intelligent system, HPC, Studio, X86, Ecosystem, PPA, Cryptocurrency, Video game, Cadence

Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced its digital and custom/analog flows are certified on the Intel 16 FinFET process technology and its design IP supports this node from Intel Foundry Services (IFS).

Key Points: 
  • Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced its digital and custom/analog flows are certified on the Intel 16 FinFET process technology and its design IP supports this node from Intel Foundry Services (IFS).
  • Customers can begin using the production-ready Cadence® design flows and design IP now to achieve design goals and speed time to market.
  • The complete Cadence RTL-to-GDS flow has been certified and optimized for use with Intel 16 technology, allowing customers to meet power, performance and area (PPA) targets.
  • Some of the Cadence flow’s capabilities for Intel 16 process rules have been enhanced, including via insertion and antenna rule support, which ensure high-quality designs.

Cadence Announces Second Quarter 2023 Financial Results Webcast

Retrieved on: 
Venerdì, Luglio 7, 2023
Software, Technology, Electronic Design Automation, Semiconductor, Cadence Design Systems, Webcast, CDNS, Management

Cadence Design Systems, Inc. (Nasdaq: CDNS) will hold its second quarter 2023 financial results webcast on Monday, July 24, 2023.

Key Points: 
  • Cadence Design Systems, Inc. (Nasdaq: CDNS) will hold its second quarter 2023 financial results webcast on Monday, July 24, 2023.
  • Participating in the webcast will be Dr. Anirudh Devgan, president and chief executive officer, and John Wall, senior vice president and chief financial officer.
  • The webcast will begin Monday, July 24, 2023 at 2:00 p.m. Pacific Time.
  • An archive of the webcast will be available online from 5:00 p.m. Pacific Time on July 24, 2023 until 5:00 p.m. Pacific Time on Friday, September 15, 2023 at cadence.com/cadence/investor_relations .

Cadence Digital and Custom/Analog Design Flows Certified for Samsung Foundry’s SF2 and SF3 Process Technologies

Retrieved on: 
Mercoledì, Giugno 28, 2023
Software, Technology, Mobile, Wireless, Hardware, Spectre, Kurdistan, Cadence Design Systems, Samsung Electronics, CDNS, Computation, SF2, Samsung, SF3, SOC, Proposed UK Internet age verification system, OpenAccess, Certification, GDS, Foundry, Studio, Digital, AI, PPA, Mobile phone, Video game, Cadence

Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that its digital and custom/analog flows achieved certification for Samsung Foundry’s SF2 and SF3 process technologies.

Key Points: 
  • Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that its digital and custom/analog flows achieved certification for Samsung Foundry’s SF2 and SF3 process technologies.
  • Joint customers are actively developing SF2- and SF3-based designs using the Cadence® flows.
  • Cadence’s comprehensive Cadence RTL-to-GDS design flow that supports Samsung’s SF2 and SF3 technologies provides optimal power, performance and area (PPA).
  • “Through our latest collaboration with Cadence, we’ve seen early customers improve productivity with the Cadence-certified design flows and our advanced SF2 and SF3 process technologies,” said Sangyun Kim, vice president of the Foundry Design Technology Team at Samsung Electronics.

Cadence Delivers Certified, Innovative Backside Implementation Flow to Support Samsung Foundry SF2 Technology

Retrieved on: 
Mercoledì, Giugno 28, 2023
Semiconductor, Electronic Design Automation, Technology, Artificial Intelligence, Software, Cadence Design Systems, Samsung Electronics, RTL, CDNS, SF2, Samsung, Proposed UK Internet age verification system, Tempus, PDK, Foundry, Digital, Silicon, AI, PPA, Mobile phone, Cadence

Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that it has delivered a complete, certified backside implementation flow to support Samsung Foundry’s SF2 process node.

Key Points: 
  • Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that it has delivered a complete, certified backside implementation flow to support Samsung Foundry’s SF2 process node.
  • This latest collaboration between Cadence and Samsung Foundry enables customers to leverage the Cadence® digital full flow and corresponding process design kit (PDK) to speed next-generation mobile, automotive, AI and hyperscale chip design innovation.
  • The complete Cadence RTL-to-GDS flow that is optimized for the Samsung Foundry 2nm process technology includes the Genus™ Synthesis Solution, Innovus™ Implementation System, Integrity™ 3D-IC platform, Quantus™ Extraction Solution, Pegasus™ Verification System, Voltus™ IC Power Integrity Solution, Tempus™ Timing Signoff Solution and Tempus ECO Option.
  • “The successful rollout of this backside design flow, fully supported by the Cadence digital flow, lets customers reap the benefits of our advanced SF2 technology.”
    “Designers can speed time to market by leveraging our collaboration with Samsung Foundry on the complete RTL-to-GDS flow and SF2 technology,” said Vivek Mishra, corporate vice president in the Digital & Signoff Group at Cadence.

Samsung Foundry Certifies Cadence Virtuoso Studio Flow to Automate Analog IP Migration on Advanced Process Technologies

Retrieved on: 
Mercoledì, Giugno 28, 2023
Electronic Design Automation, Semiconductor, Technology, Software, Artificial Intelligence, Hardware, Custom, Cadence Design Systems, Samsung Electronics, CDNS, Virtuoso, Samsung, SOC, Studio, Automation, Cryptocurrency, Printed circuit board, Cadence

Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the availability of a certified node-to-node design migration flow based on the new generative AI-powered Cadence® Virtuoso® Studio.

Key Points: 
  • Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the availability of a certified node-to-node design migration flow based on the new generative AI-powered Cadence® Virtuoso® Studio.
  • Cadence and Samsung jointly developed this new generative design migration flow to simplify and automate the process, providing mutual customers with up to a 2X productivity boost so they can get to market faster.
  • The Virtuoso Schematic Editor, part of the Virtuoso Studio, automatically maps a source schematic’s instances, parameters, pins and wiring from one process technology to another.
  • “With Samsung’s advanced process technologies and the Cadence flows, designers can benefit from increased productivity and ultimately deliver high-quality designs to market faster.”
    Cadence Virtuoso Studio supports the Cadence Intelligent System Design™ strategy, enabling system-on-chip (SoC) design excellence.

Cadence AI-Based Virtuoso Studio Certified for Samsung Foundry PDKs for Mature and Advanced Nodes

Retrieved on: 
Martedì, Giugno 27, 2023
Software, Networks, Internet, Data Management, Technology, Apps, Applications, Mobile, Wireless, Security, DFM, Custom, DRC, Kurdistan, Cadence Design Systems, Samsung Electronics, LVS, CDNS, Pegasus, Adobe InDesign, SF2, Samsung, Head, ICS, SF3, SOC, Certification, Self Control (Raf song), HMF, Hyperscale computing, PGV, Studio, AI, RF, Mobile phone, Cadence

Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that the AI-based Cadence® Virtuoso® Studio design tools and solutions have been certified by Samsung Foundry.

Key Points: 
  • Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that the AI-based Cadence® Virtuoso® Studio design tools and solutions have been certified by Samsung Foundry.
  • Joint customers can confidently leverage Virtuoso Studio and Samsung’s mature and advanced node process design kits (PDKs) down to SF2 to advance next-generation analog, custom, RF and mixed-signal design.
  • The Cadence Voltus™-XFi Custom Power Integrity Solution, also integrated with Virtuoso Studio, is also now optimized and certified for Samsung Foundry’s advanced process technologies.
  • This enables customers to confidently adopt state-of-the-art and future-ready custom IC design flow with Samsung Foundry PDKs.

Cadence Expands Collaboration with Samsung Foundry, Providing Differentiated Reference Flows Based on the Integrity 3D-IC Platform

Retrieved on: 
Martedì, Giugno 27, 2023
IOT (Internet of Things), Technology, Software, 5G, Artificial Intelligence, Hardware, PDN, DRC, Cadence Design Systems, Samsung Electronics, LVS, CDNS, Workflow, Internet of things, Samsung, SOC, Intelligent system, Integrity, 3D-IC, Hyperscale computing, Foundry, Digital, AI, CODE, Environment, Video game, Cadence

This latest collaboration advances multi-die planning and implementation with the delivery of the latest reference flows and corresponding package design kits based on the Cadence® Integrity™ 3D-IC platform, the industry’s only unified platform that includes system planning, packaging and system-level analysis in a single cockpit.

Key Points: 
  • This latest collaboration advances multi-die planning and implementation with the delivery of the latest reference flows and corresponding package design kits based on the Cadence® Integrity™ 3D-IC platform, the industry’s only unified platform that includes system planning, packaging and system-level analysis in a single cockpit.
  • In addition, the Integrity 3D-IC platform supports Samsung’s new 3D CODE standard, a new system description language that simplifies the definition and interoperability of design creation and analysis flows in a unified environment.
  • The reference flows based on the Integrity 3D-IC platform offer key capabilities, including early analysis for the power delivery network (PDN), thermal and system-level layout versus schematic (LVS) and design rule checking (DRC).
  • “The reference flows based on the Cadence Integrity 3D-IC platform combined with Samsung’s latest technologies provide our customers a unified design environment that simplifies the workflow and reduces multi-die planning and implementation turnaround time when creating complex 3D-IC designs.”
    The Cadence Integrity 3D-IC platform supports the company’s Intelligent System Design™ strategy, enabling SoC design excellence.