Memory management unit

Andes and MachineWare Collaborate on Early RISC-V Software Development for AndesCoreTM AX45MPV

Retrieved on: 
Tuesday, February 27, 2024

In this joint effort, MachineWare lends its support by seamlessly integrating the AX45MPV into their SIM-V high-performance simulation solution.

Key Points: 
  • In this joint effort, MachineWare lends its support by seamlessly integrating the AX45MPV into their SIM-V high-performance simulation solution.
  • This integration proves invaluable for software developers, enabling them to efficiently handle intricate AI and Linux stack related workloads.
  • The result is a platform that streamlines development, testing, and software verification well in advance of physical prototypes emerging from the fabrication process.
  • "We are delighted to join forces with Andes to support the AX45MPV processor in SIM-V," said Lukas Jünger, Managing Director at MachineWare.

Andes Announces RISC-V Multicore 1024-bit Vector Processor: AX45MPV

Retrieved on: 
Wednesday, December 7, 2022

The AX45MPV inherits all the features of the AX45MP and leverages the 3-year field experience of the successful Andes vector processor NX27V.

Key Points: 
  • The AX45MPV inherits all the features of the AX45MP and leverages the 3-year field experience of the successful Andes vector processor NX27V.
  • (*P is a draft version)
    The Vector Processing Unit (VPU) of the AX45MPV implements RISC-V Vector Extension (RVV) version 1.0.
  • “The AX45MPV multicore vector processor is another important milestone for Andes and RISC-V enthusiasts since our NX27V, the first RISC-V commercial vector processor and a very successful one announced 3 years ago,” said Andes Chairman and CEO, Frankwell Lin.
  • It is exciting to see AX45MPV perfectly satisfy their expectations.”
    “Multicore vector processors are designed for applications with high parallelism.

Andes RISC-V Superscalar Multicore A(X)45MP and Vector Processor NX27V Upgrade Their Spec. and Performance

Retrieved on: 
Thursday, December 2, 2021

The latency for Level-1 Cache miss and Level-2 Cache hit is reduced by half and it leads to the outstanding 3.4 SPECint2006/GHz performance.

Key Points: 
  • The latency for Level-1 Cache miss and Level-2 Cache hit is reduced by half and it leads to the outstanding 3.4 SPECint2006/GHz performance.
  • The NX27V, supporting the RISC-V Vector Extension (RVV) spec v1.0-rc1, is upgraded with full configurations of 128-bit to 512-bit VLEN/SIMD/MEM.
  • The industrial leading NX27V vector processor just got another award, the EDA & IP Product Award from EE Times (Nov. 16).
  • Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities.