Intelligent system

Cadence Reports Fourth Quarter and Fiscal Year 2023 Financial Results

Retrieved on: 
Monday, February 12, 2024

Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced results for the fourth quarter and fiscal year 2023.

Key Points: 
  • Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced results for the fourth quarter and fiscal year 2023.
  • “I'm thrilled about the opportunities ahead of us, particularly in AI and 3D-IC.
  • “I’m pleased with our record year-end backlog of $6.0 billion and cRPO of $3.2 billion, and I look forward to building on that strength in 2024.”
    Commentary on the fourth quarter and fiscal year 2023 financial results by John Wall, senior vice president and chief financial officer, is available at www.cadence.com/cadence/investor_relations .
  • For the first quarter of 2024, the company expects:
    The company utilizes a long-term projected non-GAAP tax rate, which reflects currently available information, as well as other factors and assumptions.

After another record year ahead of expectations, Publicis unveils AI strategy to lead group into its second century

Retrieved on: 
Thursday, January 25, 2024

In the last 6 years, Publicis has truly become a partner in its clients’ transformation.

Key Points: 
  • In the last 6 years, Publicis has truly become a partner in its clients’ transformation.
  • That platform organization has allowed Publicis to outperform the market on both financial and extra-financial KPIs.
  • Concretely, Publicis is infusing a layer of AI across its platform organization to connect its enterprise knowledge under one entity: CoreAI.
  • Publicis plans to invest three hundred million euros over the next three years as it becomes a true Intelligent System.

Cadence Unveils New Palladium Z2 Apps with Industry’s First 4-State Emulation and Mixed-Signal Modeling to Accelerate SoC Verification

Retrieved on: 
Thursday, January 18, 2024

The new Cadence® apps and updates individually offer industry-leading performance and features to address these growing challenges.

Key Points: 
  • The new Cadence® apps and updates individually offer industry-leading performance and features to address these growing challenges.
  • “NVIDIA has utilized Cadence Palladium Emulation for many years for our early software development, hardware-software verification and debug tasks.
  • We have worked closely with Cadence to provide input on the new Palladium apps, including the industry’s first Real Number Modeling and 4-State Emulation apps.
  • With the new 4-State Emulation App, we can accelerate the low-power verification of our complex SoC designs, improving our verification accuracy and low-power coverage while improving overall verification throughput.”​

Cadence Signoff Solutions Empower Samsung Foundry’s Breakthrough Success on 5G Networking SoC Design

Retrieved on: 
Thursday, November 30, 2023

Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that Samsung Foundry successfully taped out a 5G networking SoC design on the Samsung 5LPE technology using the Cadence® Quantus™ Extraction Solution and Tempus™ Timing Solution.

Key Points: 
  • Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that Samsung Foundry successfully taped out a 5G networking SoC design on the Samsung 5LPE technology using the Cadence® Quantus™ Extraction Solution and Tempus™ Timing Solution.
  • This accomplishment marks a turning point for Samsung Foundry where the team deployed the Cadence signoff solutions for the first time, achieving a 2X productivity boost that led to faster design closure versus its previous design methodology.
  • The team also experienced significant power, performance and area (PPA) gains on this 120M instance design using the Cadence integrated flow.
  • The tools and flow support the company’s Intelligent System Design™ strategy, enabling customers to achieve SoC design excellence.

Realtek Deploys Cadence Tempus Timing Solution to Deliver Working Silicon on N12 Design

Retrieved on: 
Tuesday, October 31, 2023

Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that Realtek successfully used the Cadence® Tempus™ Timing Solution to sign off an N12 high-performance CPU core while achieving significantly improved power, performance and area (PPA).

Key Points: 
  • Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that Realtek successfully used the Cadence® Tempus™ Timing Solution to sign off an N12 high-performance CPU core while achieving significantly improved power, performance and area (PPA).
  • By adopting the Tempus Timing Solution, Realtek realized a 2X boost in productivity and reduced design closure turnaround time by 50% versus their previous methodology.
  • Cadence signoff solutions provided the Realtek team with several key benefits, including:
    Accurate golden signoff analysis: Cadence’s Tempus Timing Solution and Quantus™ Extraction Solution empowered the Realtek team to confidently deliver accurate, working silicon
    Improved productivity and reduced schedule time: The Tempus ECO Option with SmartMMMC Optimization enabled Realtek to converge timing closure faster with fewer iterations from within the Innovus™ Implementation System
    “Meeting our time-to-market deadlines with optimally performing parts is crucial to our business, and the Cadence Tempus Timing Solution helped us achieve those goals,” said Yee-Wei Huang, vice president at Realtek.
  • The Tempus Timing Solution and digital full flow support the company’s Intelligent System Design™ strategy, accelerating SoC design excellence.

Cadence Completes Acquisition of PHY IP Assets from Rambus

Retrieved on: 
Thursday, September 7, 2023

Cadence Design Systems, Inc. (Nasdaq: CDNS) announced today that it has completed the previously announced acquisition of the SerDes and memory interface PHY IP business from Rambus Inc. With the continued proliferation of AI, data center and hyperscale applications, CPU architectures, and networking devices, the technology asset purchase enriches Cadence’s established IP portfolio and augments the company’s Intelligent System Design™ strategy, which drives design excellence.

Key Points: 
  • Cadence Design Systems, Inc. (Nasdaq: CDNS) announced today that it has completed the previously announced acquisition of the SerDes and memory interface PHY IP business from Rambus Inc. With the continued proliferation of AI, data center and hyperscale applications, CPU architectures, and networking devices, the technology asset purchase enriches Cadence’s established IP portfolio and augments the company’s Intelligent System Design™ strategy, which drives design excellence.
  • The acquisition also comes with the addition of experienced PHY engineering teams in the United States, India and Canada, further expanding Cadence’s domain-rich talent base.

Cadence, GlobalFoundries, Hoerzentrum Oldenburg and Leibniz University Hannover Collaborate to Advance Hearing Aid Technology

Retrieved on: 
Tuesday, July 18, 2023

The SmartHeAP SoC prototype provides hearing aid companies with all the components required to create and reprogram hearing devices that improve a wearer’s hearing experience.

Key Points: 
  • The SmartHeAP SoC prototype provides hearing aid companies with all the components required to create and reprogram hearing devices that improve a wearer’s hearing experience.
  • Cost Savings: The hearing aid software can be quickly upgraded without replacing the hardware, saving both the wearers and the hearing aid companies money.
  • “The collaboration between GF, Cadence, Hoerzentrum Oldenburg gGmbH and Leibniz University Hannover resulted in a successful hearing aid SoC that consumes significantly less power while providing hearing aid wearers with the first-of-its-kind binaural technology that transforms how they process a complete auditory scene.
  • By collaborating with Cadence, GF and Hoerzentrum Oldenburg gGmbH, we’re bringing the joy of hearing back to hearing aid wearers with this new SoC prototype.”

Cadence Unveils Joules RTL Design Studio, Delivering Breakthrough Gains in RTL Productivity and Quality of Results

Retrieved on: 
Friday, July 14, 2023

Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the delivery of the Cadence® Joules™ RTL Design Studio, a new solution that provides users with actionable intelligence to accelerate the register transfer level (RTL) design and implementation process.

Key Points: 
  • Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the delivery of the Cadence® Joules™ RTL Design Studio, a new solution that provides users with actionable intelligence to accelerate the register transfer level (RTL) design and implementation process.
  • With Joules RTL Design Studio, users can achieve physical estimates quickly and accurately, unlocking up to 5X productivity and up to 25% quality of results (QoR) improvements in the RTL.
  • View the full release here: https://www.businesswire.com/news/home/20230713175152/en/
    The new Cadence Joules RTL Design Studio provides users with actionable intelligence to accelerate the register transfer level (RTL) design and implementation process, delivering up to 5X faster RTL convergence and up to 25% improved QoR.
  • Now, by leveraging Joules RTL Design Studio from Cadence, we can achieve efficient and accurate power breakdown analysis much earlier in the design phase.

Cadence Digital, Custom/Analog Design Flows Certified and Design IP Available for Intel 16 FinFET Process

Retrieved on: 
Tuesday, July 11, 2023

Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced its digital and custom/analog flows are certified on the Intel 16 FinFET process technology and its design IP supports this node from Intel Foundry Services (IFS).

Key Points: 
  • Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced its digital and custom/analog flows are certified on the Intel 16 FinFET process technology and its design IP supports this node from Intel Foundry Services (IFS).
  • Customers can begin using the production-ready Cadence® design flows and design IP now to achieve design goals and speed time to market.
  • The complete Cadence RTL-to-GDS flow has been certified and optimized for use with Intel 16 technology, allowing customers to meet power, performance and area (PPA) targets.
  • Some of the Cadence flow’s capabilities for Intel 16 process rules have been enhanced, including via insertion and antenna rule support, which ensure high-quality designs.

AI in chip design: Where does Cadence stand?

Retrieved on: 
Friday, June 30, 2023

KT Moore, the vice president of Corporate Marketing at Cadence, will speak at the event about optimizing performance from chips to systems with generative AI.

Key Points: 
  • KT Moore, the vice president of Corporate Marketing at Cadence, will speak at the event about optimizing performance from chips to systems with generative AI.
  • In a preliminary interview with DIGITIMES Asia, the Cadence VP also shares his views on AI deployment in chip design and its implications for the company.
  • According to Moore, Cadence already anticipated the growing role of AI in chip design approximately ten years ago.
  • "It's possible that AI can design a chip, but I think we have a lot more learning to do."