IP Group

BERGER MONTAGUE ANNOUNCES LAUNCH OF FULL-SERVICE INTELLECTUAL PROPERTY PRACTICE

Retrieved on: 
Wednesday, June 21, 2023
ABA, Patent, Intellectual property, State, Pennsylvania Bar Association, U.S. Department of Defense Strategy for Operating in Cyberspace, Education, Health, Private law, Electronics, Internet, Culture, Senior counsel, Bureau of Medical Services (U.S. Department of State), Biotechnology, Bard (company), IP Group, Lawyer, IP, Creativity, Sale, Digital technology, Ethics, Legal ethics, Diversity, Professional, Architecture, Artificial intelligence, Inclusion, Real estate, Pharmaceutical industry, Creative industries, Insurance, 3D printing, Counsel

PHILADELPHIA, June 21, 2023 /PRNewswire/ -- Berger Montague is pleased to announce that effective today, it has added one of the leading intellectual property groups in the country to represent clients worldwide in all facets of intellectual property law. In doing so, Berger Montague, an award-winning national complex litigation firm, will fill a critical need in the marketplace for a full-service IP firm that can represent clients in all their IP legal needs on a cost-effective basis. The new practice area is opening with a group of seven senior IP lawyers plus staff, who have joined Berger Montague after leaving a large defense-side law firm in Philadelphia.

Key Points: 
  • By retaining Berger Montague for their IP legal needs, clients will benefit from more personalized, boutique, and bespoke service.
  • Berger Montague Chairman Eric L. Cramer stated, "We're thrilled to be building out an intellectual property and patent infringement litigation practice at Berger Montague, and there isn't a better group of attorneys than Alfred's team to usher the firm into this area of law.
  • Mr. Haleva focuses his practice on intellectual property litigation, as well as patent and trademark preparation and prosecution in various industries.
  • Berger Montague encourages U.S. and international businesses and individuals to contact the firm for more information concerning representation in intellectual property matters, including patents, trademarks, copyrights, trade secrets, and domain names.

Cadence and Samsung Foundry Enter Multi-Year Agreement to Expand Design IP Portfolio

Retrieved on: 
Wednesday, June 14, 2023
Technology, Hardware, Electronic Design Automation, Semiconductor, Cadence Design Systems, IP Group, PHY, CDNS, Samsung Electronics, EDA, EVP, Computation, Samsung, SF3, SOC, IP, DDR5, PCI, GDDR6, HPC, Ecosystem, PPA, Mobile phone, Cadence

Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced ​​that it has signed a multi-year agreement with Samsung Foundry to expand the availability of Cadence’s design IP portfolio on Samsung Foundry’s SF5A process technology, the latest 5nm process variant to support automotive applications.

Key Points: 
  • Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced ​​that it has signed a multi-year agreement with Samsung Foundry to expand the availability of Cadence’s design IP portfolio on Samsung Foundry’s SF5A process technology, the latest 5nm process variant to support automotive applications.
  • The Cadence® design IP solution delivers optimal power, performance, and area (PPA) with rich feature sets to enable uncompromised differentiation, versatility, and innovation for large-scale SoC designs.
  • “Cadence and Samsung have been collaborating closely on Samsung EDA and IP ecosystem enablement for years.
  • “Cadence is committed to expanding our IP portfolio to address our customers’ evolving design requirements,” said Rishi Chugh, vice president of product marketing in the IP Group at Cadence.

IPS Group Demonstrates Advantages of Fully Integrated Smart Parking Ecosystem at IPMI Parking & Mobility Conference

Retrieved on: 
Monday, June 12, 2023
University, Smart Parks, SAN, IP Group, Ecosystem, Conference, IPS, Mobile phone, Online shopping

SAN DIEGO, June 12, 2023 /PRNewswire/ -- IPS Group ("IPS"), a Smart Parking innovation leader, will demonstrate at the IPMI Parking & Mobility Conference & Expo in Fort Worth, TX June 11 – 14, 2023 how the Fully Integrated Smart Parking Ecosystem streamlines operations in a seamless experience.

Key Points: 
  • End-to-end technology portfolio delivers enhanced user experience, boosts process efficiencies and performance measurement across entire on-street and off-street parking programs for municipalities, universities, and other agencies
    SAN DIEGO, June 12, 2023 /PRNewswire/ -- IPS Group ("IPS"), a Smart Parking innovation leader, will demonstrate at the IPMI Parking & Mobility Conference & Expo in Fort Worth, TX June 11 – 14, 2023 how the Fully Integrated Smart Parking Ecosystem streamlines operations in a seamless experience.
  • The IPS portfolio connects parking control, citations, mobile and digital payment, and frictionless parking solutions
    Parking professionals accelerate their productivity and deliver a superior end-user experience with the Fully Integrated Smart Parking Ecosystem – an end-to-end management and business intelligence solution that connects a comprehensive technology portfolio of parking revenue control, parking violations and collections, mobile and digital payments, and frictionless parking solutions by IPS.
  • "Most agencies today continue to face the age-old need of delivering better service with fewer resources," says Chad Randall, CEO, IPS Group.
  • The IPS Fully Integrated Smart Parking Ecosystem connects technology that was built from the ground up, together, to enable a common user experience, operational efficiencies, and scalability.

AccelerComm Secures £21.5m Series B Funding from Parkwalk, Swisscom, Hostplus and Existing investors IQ Capital, Bloc Ventures and IP Group to Supercharge 5G Radio Performance

Retrieved on: 
Thursday, May 11, 2023
Technology, Satellite, Mobile, Wireless, Telecommunications, 5G, Networks, National Instruments, University, Noise, AMD, ARM, Dengeki G's Radio, IP Group, Ericsson, Qualcomm, IP, Hostplus, Mobile World Congress, LEO, Intel, Radio, Vodafone, Growth, EE Times, L1, Swisscom, Series

AccelerComm, the company with IP which optimizes 5G radio access network performance, today announced it has closed £21.5m in Series B funding from Parkwalk, Swisscom and Hostplus together with participation from existing investors Bloc Ventures, IP Group and IQ Capital.

Key Points: 
  • AccelerComm, the company with IP which optimizes 5G radio access network performance, today announced it has closed £21.5m in Series B funding from Parkwalk, Swisscom and Hostplus together with participation from existing investors Bloc Ventures, IP Group and IQ Capital.
  • AccelerComm’s award-winning 5G channel coding IP is used to correct mobile transmission errors caused by noise, interference and poor signal strength.
  • This technology is highly configurable and can be optimized for the specific needs of both terrestrial and satellite communications to provide market-leading performance and efficiency.
  • This level of funding will help the company realize its commercial potential, promising a step-change moment in the development and capability of 5G satellite technology.

Cadence Collaborates with GUC on AI, HPC and Networking in Advanced Packaging Technologies

Retrieved on: 
Wednesday, April 26, 2023
Networks, Semiconductor, Hardware, Electronic Design Automation, Technology, Cadence Design Systems, IP Group, PHY, CDNS, DSP, SerDes, HBM3, NRZ, IP, SOC, Intelligent system, CPU, HPC, TSMC, ADC, AI, GUC, Silicon, GPU, Video game, Medical device, Cadence, PAM4

Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that the Cadence® 112G-LR SerDes is silicon proven on the HBM3/GLink/CoWoS platform from Global Unichip Corp. (GUC).

Key Points: 
  • Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that the Cadence® 112G-LR SerDes is silicon proven on the HBM3/GLink/CoWoS platform from Global Unichip Corp. (GUC).
  • The 112G-LR SerDes has been validated in the GUC CoWoS platform, demonstrating excellent performance and robustness in large-scale AI/HPC/networking chip conditions.
  • “The Cadence 112G-LR/ELR PAM4 SerDes IP portfolio has been widely adopted by customers to enable AI, HPC, networking and 5G SoC designs.
  • The 112G-LR SerDes IP is part of the broader Cadence IP portfolio and supports the company’s Intelligent System Design Strategy, enabling SoC design excellence.

Cadence Accelerates Hyperscale SoC Design with Next-Generation 112G Extended Long-Reach SerDes IP on TSMC’s N4P Process

Retrieved on: 
Monday, April 24, 2023
Electronic Design Automation, Data Management, Semiconductor, Technology, 5G, Networks, Hardware, Application-specific integrated circuit, Cadence Design Systems, IP Group, CDNS, DSP, SerDes, Computation, NRZ, LR, IP, SOC, DAC, IEEE, PAM4, Socs, BER, TSMC, Insertion loss, ELR, Silicon, Architecture, VSR, Video game, Cadence

Cadence Design Systems, Inc. (Nasdaq: CDNS) today unveiled its 112G Extended Long-Reach (112G-ELR) SerDes IP on TSMC’s N4P process for hyperscale ASICs, artificial intelligence/machine learning (AI/ML) accelerators, switch fabric system-on-chips (SoCs) and 5G wireless infrastructure.

Key Points: 
  • Cadence Design Systems, Inc. (Nasdaq: CDNS) today unveiled its 112G Extended Long-Reach (112G-ELR) SerDes IP on TSMC’s N4P process for hyperscale ASICs, artificial intelligence/machine learning (AI/ML) accelerators, switch fabric system-on-chips (SoCs) and 5G wireless infrastructure.
  • The Cadence® 112G-ELR SerDes PHY IP on TSMC’s N4P process, a performance-focused enhancement of the TSMC 5nm technology platform, incorporates industry-leading digital signal processor (DSP)-based SerDes architecture with maximum likelihood sequence detection (MLSD) and reflection cancellation technology.
  • The SerDes PHY IP is compliant with IEEE and OIF Long-Reach (LR) standards while providing extra performance margin for ELR applications.
  • The 112G-ELR SerDes PHY IP on TSMC’s N4P process is part of the broader Cadence IP portfolio and supports the Cadence Intelligent System Design™ strategy, which enables advanced-node SoC design excellence.

Cadence Tapes Out 16G UCIe Advanced Package IP on TSMC’s N3E Process Technology

Retrieved on: 
Monday, April 24, 2023
Internet, Hardware, Consumer Electronics, Technology, Software, Cadence Design Systems, CXL, IP Group, PHY, CDNS, TLM, SIP, RDL, SOC, PCI, Socs, TSMC, Silicon, Ecosystem, VIP, Video game, Cadence, IP, UCIe

Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the tapeout of Cadence® 16G UCIe™ 2.5D advanced package IP on TSMC’s 3nm (N3E) process technology.

Key Points: 
  • Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the tapeout of Cadence® 16G UCIe™ 2.5D advanced package IP on TSMC’s 3nm (N3E) process technology.
  • Implemented on TSMC’s 3DFabric™ CoWoS-S silicon interposer technology, the IP offers ultra-high bandwidth density, efficient low-power performance and superior low latency, making it ideal for applications requiring extreme compute power.
  • Cadence is currently engaged with a pipeline of Tier 1 customers, and UCIe advanced package IP collateral from the N3E test chip tapeout is shipping and available.
  • The recent UCIe advanced package tapeout on the TSMC N3E process is a key milestone and commitment toward enabling customers with an open chiplet connectivity standard.”
    The Cadence 16G UCIe™ 2.5D advanced package IP supports Cadence’s Intelligent System Design™ strategy, which enables SoC design excellence.

Lathrop GPM LLP Intellectual Property Group Expands in Boston and Minneapolis

Retrieved on: 
Thursday, April 20, 2023
Molecular biology, Employment Law Alliance, Intellectual property, Florida College, University, D, Doctor of Philosophy, Pharming, Senior counsel, Biotechnology, Leadership Council, Arnold, IP Group, University of Minnesota School of Dentistry, Research, Lawyer, Arnold and Marie Schwartz College of Pharmacy, IP, Boston University, Food microbiology, Multimedia, Messenger, Fordham University School of Law, Tulane University, Employment, DE, Oshkosh, Public health, Patent, Montclair State University, Certification, Growth, Jan Vansina, Synthetic biology, Creative industries, Pharmaceutical industry, Pharmacy, Microbiology, Chemistry, Cell, Pharmacology

BOSTON, April 20, 2023 /PRNewswire/ -- Lathrop GPM LLP add four lawyers to the Intellectual Property Practice Group in Boston and Minneapolis.

Key Points: 
  • BOSTON, April 20, 2023 /PRNewswire/ -- Lathrop GPM LLP add four lawyers to the Intellectual Property Practice Group in Boston and Minneapolis.
  • Lathrop GPM's Intellectual Property Group includes more than 75 practitioners across the U.S.
    IP and life sciences continue to be a key focus of our growth.
  • "This is an exciting time of expansion for our IP team," said Kate Tompkins , leader of the firm's IP Group.
  • Lathrop GPM is a full-service, Am Law 200 law firm with more than 325 attorneys in 12 offices.

Cadence Demonstrates Interoperability with SK hynix’s Highest Speed LPDDR5T Mobile DRAM at 9600Mbps

Retrieved on: 
Monday, April 17, 2023
Mobile, Wireless, Technology, Semiconductor, 5G, Software, Hardware, Electronic Design Automation, Data Management, Consumer Electronics, Artificial Intelligence, Cadence Design Systems, SK, IP Group, PHY, LPDDR5, CDNS, DRAM, SOC, LPDDR5X, GDDR6, Machine learning, Architecture, Memory, Video game, Turbocharger, Cadence

Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that it has demonstrated interoperability between the silicon-proven Cadence® LPDDR5X memory interface IP and SK hynix’s LPDDR5T (Turbo) mobile DRAM, operating at speeds in excess of the LPDDR5X standard.

Key Points: 
  • Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that it has demonstrated interoperability between the silicon-proven Cadence® LPDDR5X memory interface IP and SK hynix’s LPDDR5T (Turbo) mobile DRAM, operating at speeds in excess of the LPDDR5X standard.
  • This milestone follows Cadence’s earlier announcement of the first LPDDR5X memory interface IP design operating at 8533Mbps and SK hynix’s first announcement of its LPDDR5T mobile DRAM technology operating at 9600Mbps.
  • “SK hynix’s LPDDR5 Turbo mobile DRAM opens up new possibilities beyond smartphones, to AI, machine learning and augmented/virtual reality,” said Sungsoo Ryu, VP of DRAM product planning at SK hynix.
  • “Proving interoperability with Cadence’s memory interface IP is a key step in enabling customers targeting 9600Mbps operation.”
    “Cadence LPDDR5X design IP implements the highest performance signal-boosting design techniques,” noted Sanjive Agarwala, corporate vice president and general manager of the IP Group at Cadence.

Fluidra Proposes a Dividend Distribution of 0.70 Euros Per Share

Retrieved on: 
Friday, March 31, 2023
Manufacturing, Other Retail, Retail, Specialty, Chemicals, Plastics, Vice, London Stock Exchange, Marketing, Policy, IP Group, RACC, Advisory board, Georgetown University, Organization, London, Trustee, Supervisory board, ESG, Jackson Family Wines, Remuneration, Holding company, Management, Puig, Fluidra

The proposal implies a 50% payout of 2022 Cash EPS, in line with Fluidra’s dividend policy.

Key Points: 
  • The proposal implies a 50% payout of 2022 Cash EPS, in line with Fluidra’s dividend policy.
  • The total payout, subject to approval by the General Shareholders' Meeting to be held on 10 May, will amount to 134 million euros.
  • If approved, Fluidra will make a first payment of 0.35 euros per share on 5 July and another payment of the same amount on 5 December 2023.
  • Since it resumed dividend payments in October 2020, it has distributed 1.46 euros per share, to which 0.70 euros per share will be added if approved at the General Shareholders' Meeting.