FR-V

MEDIA ALERT: Join Andes Principle Architect Dr. Thang Tran's Lecture, "Demystifying RISC-V Vector Extension"

Retrieved on: 
Friday, July 9, 2021
Parallel computing, Computer architecture, Computing, Computers, Central processing unit, Classes of computers, Superscalar processor, Vector processor, Scalar processor, FR-V

The hour long event will be the first of a 4-part lecture series on next-generation vector processor design.

Key Points: 
  • The hour long event will be the first of a 4-part lecture series on next-generation vector processor design.
  • It will showcase a 5-stage pipeline and an 8-stage in-order superscalar vector processor based on Andes latest AndeStar V5 Architecture.
  • Who: Dr. Thang Tran, Principal Architect and veteran of high-performance computing (HPC) at Andes Technology Corp. will be the series' presenter.
  • The vector processor issues 8 micro-ops per cycle with up to 14 vector instructions in parallel execution.