Cache coherence

Breker Verification Systems Joins RISC-V International as a Strategic Member to Drive Cache Coherency and SoC Integration Verification Methodologies

Retrieved on: 
Thursday, June 30, 2022
Analog Devices, Security, DAC, CEO, Design Automation Conference, International, Huawei, GLOBE, Second, Moscone Center, RVI, Post-silicon validation, Industry, VIP, ISA, SAN, Cache coherence, ARM, UVM, Intel, C, Solution, IBM, PSS, Leadership, Algorithm, Conference, Video game console, Risk management, Arno Breker, SOC, Altera, Broadcom Inc.

SAN JOSE, Calif., June 30, 2022 (GLOBE NEWSWIRE) -- Breker Verification Systems , the leading provider of advanced test content synthesis solutions, including RISC-V Cache Coherency and other SoC integration Verification Intellectual Property (VIP) in the TrekApps family, today joined RISC-V International (RVI) as a strategic member.

Key Points: 
  • SAN JOSE, Calif., June 30, 2022 (GLOBE NEWSWIRE) -- Breker Verification Systems , the leading provider of advanced test content synthesis solutions, including RISC-V Cache Coherency and other SoC integration Verification Intellectual Property (VIP) in the TrekApps family, today joined RISC-V International (RVI) as a strategic member.
  • Breker will offer its expertise in SoC verification solutions to the RVI working groups.
  • Breker became a member to influence the development of a cache coherency and integration test content platform for RISC-V processor development and end-use verification.
  • Breker Verification Systems is a leading provider of Portable Stimulus solutions, a standard means to specify verification intent and behaviors reusable across target platforms.

Synopsys DesignWare CXL IP Supports AMBA CXS Protocol Targeting High-Performance Computing SoCs

Retrieved on: 
Thursday, October 8, 2020
Computing, Computer engineering, Acorn Computers, Computer science, Instruction set architectures, ARM Holdings, Nvidia, SoftBank Group, Advanced Microcontroller Bus Architecture, ARM architecture, Cache coherence, System on a chip

The Synopsys CXL IP, operating at 32GT/s with 512-bit data width, supports all required CXL protocols and device types to meet specific application requirements

Key Points: 
  • The Synopsys CXL IP, operating at 32GT/s with 512-bit data width, supports all required CXL protocols and device types to meet specific application requirements
    The industry-first CXL IP complete solution encompasses configurable controller, 32GT/s PHYs in a range of FinFET processes, and verification IP
    Synopsys, Inc. (Nasdaq: SNPS)today announced that its DesignWare CXL Controller IP now supports the AMBA CXS protocol, enabling an efficient interface with the latest, highly scalable Arm Neoverse Coherent Mesh Network to provide an optimized multichip IP stack for a range of high-performance computing, datacenter, and networking system-on-chip (SoCs).
  • The DesignWare CXL Controller supports all the required CXL protocol types (.cache, .io, and .mem) and allows mixing multiple types within a single clock-cycle transfer for design flexibility.
  • Support for CXS enables the extremely low-latency, high-bandwidth DesignWare CXL IP to extend its capabilities across Arm-based SoCs requiring cache coherency and fast chip-to-chip interconnects.
  • "By providing support for the AMBA CXS protocol, designers can easily interface Synopsys' DesignWare CXL IP to the Arm Coherent Mesh Network platform to meet the high-bandwidth requirements of their data-intensive Arm-based SoC designs."