SiFive and Barcelona Supercomputing Center Advance Industry Adoption of RISC-V Vector Extension
Retrieved on:
Thursday, September 3, 2020
Technology, Semiconductor, Security, Other Technology, Software, Networks, Hardware, Electronic design automation, Data management, Computer architecture, Computing, Microprocessors, Instruction set architectures, Fabless semiconductor companies, SiFive, Classes of computers, Parallel computing, RISC-V, Chris Lattner, Reduced instruction set computer, LLVM
In collaboration with the Barcelona Supercomputing Center, SiFive created an API for vector intrinsics for popular open-source compilers GCC, and LLVM.
Key Points:
- In collaboration with the Barcelona Supercomputing Center, SiFive created an API for vector intrinsics for popular open-source compilers GCC, and LLVM.
- Additionally, SiFive reports that the SiFive Shield Hardware Cryptographic Accelerator (HCA) true random number generator (TRNG) has successfully passed conformance evaluation to SP 800-90B standard, to enable FIPS 140 certified security solutions.
- The new API will speed up the development of vector processor applications using RISC-V processor cores with RISC-V Vector Extension (RVV) 1.0 support, such as the upcoming SiFive Intelligence line of products.
- The RISC-V Vector extension will enable new RISC-V based processor designs to accelerate many workloads, from AI to signal processing and scientific research, said Chris Lattner, President of Platform Engineering, SiFive.