SRAM

GigaDevice Launches GD32F5 Series Cortex®-M33 Core MCUs for High-Performance Applications

Retrieved on: 
Tuesday, April 9, 2024
ECC, GD32, GigaDevice, RWW, SRAM, DSP, OTA, SDRAM, IAR, IEC61508, Communication, SDIO, PLC, GUI, MCU, Software, Power management, OTG, Spacecraft, PWM, Update, Flash, Programmable logic controller, Sensor, Ecosystem, The, Automotive engineering, FMEDA, KEIL, Video game

The GD32F5 series high-performance MCUs offer significantly expanded storage space, excellent processing efficiency, and a wide array of interface options.

Key Points: 
  • The GD32F5 series high-performance MCUs offer significantly expanded storage space, excellent processing efficiency, and a wide array of interface options.
  • The GD32F5 series high-performance MCUs adopt the Arm® Cortex® -M33 core with a maximum operating frequency of 200MHz and a working performance of up to 3.31 CoreMark®/MHz.
  • The GD32F5 series high-performance MCUs are equipped with up to 7.5MB on-chip Flash and 1MB SRAM.
  • GigaDevice provides the new high-performance GD32F5 series MCU with free development environment GD32 IDE, debugging and download tool GD-LINK, and the programming tool GD32 All-In-One Programmer.

Microchip Technology Expands Its Serial SRAM Portfolio to Larger Densities and Increased Speeds

Retrieved on: 
Thursday, March 28, 2024
SRAM, SPI, MB, MCU, Microchip Technology, MCHP, RAM, SDI, SQI, Integrated circuit, Computer data storage

CHANDLER, Ariz., March 28, 2024 (GLOBE NEWSWIRE) -- To address a common customer need for bigger and faster SRAM, Microchip Technology (Nasdaq: MCHP) has expanded its Serial SRAM product line to include larger densities of up to 4 Mb and increased Serial Peripheral Interface/Serial Quad I/O™ Interface (SPI/SQI™) speed to 143 MHz.

Key Points: 
  • CHANDLER, Ariz., March 28, 2024 (GLOBE NEWSWIRE) -- To address a common customer need for bigger and faster SRAM, Microchip Technology (Nasdaq: MCHP) has expanded its Serial SRAM product line to include larger densities of up to 4 Mb and increased Serial Peripheral Interface/Serial Quad I/O™ Interface (SPI/SQI™) speed to 143 MHz.
  • This reduces the need for a more expensive, high-pin-count MCU and can help minimize the overall board footprint.
  • The 2 Mb and 4 Mb serial SRAM devices are available starting at $1.60 each in 10,000-unit quantities.
  • For additional information and to purchase, contact a Microchip sales representative, authorized worldwide distributor or visit Microchip’s Purchasing and Client Services website, www.microchipdirect.com .

Ambiq Apollo510 Delivers 30x Power Efficiency Improvement to Unleash Endpoint AI

Retrieved on: 
Tuesday, March 26, 2024
Cortex, Arm, Health, Speech, Socs, SRAM, GM, GPU, VR, Hardware, Acceleration, Intelligence, Agriculture, Internet of things, Business, SVP, MCU, AI, Software, Human, TEE, Memory, ARM architecture family, Macs, TCM, OTP, SPOT, PUF, Family, MIP, NVM, Consumer electronics

AUSTIN, Texas, March 26, 2024 (GLOBE NEWSWIRE) -- Ambiq, a technology leader in exceptionally energy-efficient semiconductors for IoT devices, is introducing the new Apollo510, the first member of the Apollo5 SoC family, which is uniquely positioned to kickstart the age of truly ubiquitous, practical, and meaningful AI.

Key Points: 
  • The Apollo510 achieves up to 10x better latency while reducing energy consumption by around 2x, compared to Ambiq's previous power efficiency leader, the Apollo4.
  • With more than 30x energy improvement, the Apollo510 is capable of running a vast majority of today's endpoint AI calculations, including low-power sensor monitoring, always-on voice commands, telco-quality audio enhancement, and more.
  • Apollo510 contains everything needed for driving intelligent systems: ultra-efficient compute, expansive on-chip memories, high-bandwidth interfaces to off-chip memories, and security.
  • IoT endpoint device manufacturers can expect unrivaled power efficiency to develop more capable devices that process AI/ML functions better than before.

SparkFun Electronics And Renesas Launch Thing Plus - RA6M5: A Developer Board For Prototyping Advanced IoT Solutions

Retrieved on: 
Tuesday, April 9, 2024
SRAM, Communication, Internet of things, Embedded, Renesas Electronics, Student, SparkFun Electronics, Electronics, Multimedia, Online shopping

BOULDER, Colo., April 9, 2024 /PRNewswire/ -- SparkFun Electronics is excited to announce the Thing Plus - RA6M5, boasting an impressive and nimble feature set designed to save developers time. The RA6M5 group from Renesas is made to meet the demands of real-time applications, featuring a 200MHz clock speed and powered by a low-power Arm® Cortex®-M33 processor.  A standout feature of the Thing Plus -RA6M5 is its Bluetooth® Low Energy connectivity. The added DA14531MOD module from Renesas facilitates wireless communication while maintaining low power consumption, using just 4mA and capable of being powered by a coin-cell battery.

Key Points: 
  • BOULDER, Colo., April 9, 2024 /PRNewswire/ -- SparkFun Electronics is excited to announce the Thing Plus - RA6M5 , boasting an impressive and nimble feature set designed to save developers time.
  • A standout feature of the Thing Plus -RA6M5 is its Bluetooth® Low Energy connectivity.
  • "With our release of the Thing Plus - RA6M5, there's no compromise between performance, low-energy consumption, and flexibility," said Kirk Benell, CTO at SparkFun Electronics.
  • "We are excited to witness the launch of the Thing Plus - RA6M5.

STMicroelectronics’ high-performance microcontrollers pave the way to new innovations in smart home and industrial systems

Retrieved on: 
Tuesday, March 12, 2024
Cortex, Research, Arm, PMIC, ICS, SRAM, UI, ARM Cortex-M, MPU, Algorithm, DTR, Communication, Patent, Internet of things, BOM, Internet, Electronics, MCU, 3D, Software, United States patent law, EHealth, MCE, Animation, PCB, Ecosystem, STM, General-purpose, STM32, STMicroelectronics, PSA, Family, CPU, Video game

Examples include adding richer, colorful user interfaces and performing multiple functions simultaneously, which is usually achieved with microprocessors (MPU).

Key Points: 
  • Examples include adding richer, colorful user interfaces and performing multiple functions simultaneously, which is usually achieved with microprocessors (MPU).
  • “The MCUs promise to enhance the visual performance and responsiveness of future displays, enabling more engaging and interactive user experiences.
  • In addition, power management is integrated on-chip, in contrast with typical MPU practice that requires an external power-management IC (PMIC).
  • STM32 is a registered and/or unregistered trademark of STMicroelectronics International NV or its affiliates in the EU and/or elsewhere.

Renesas Introduces Industry’s First General-Purpose 32-bit RISC-V MCUs with Internally Developed CPU Core

Retrieved on: 
Tuesday, March 26, 2024
Apps, Applications, Mobile, Wireless, Technology, Semiconductor, Software, Networks, Internet, Hardware, Electronic Design Automation, Data Management, ISA, FPB, SRAM, Documentation, Face, Growth, Computing, Flasher, Memory, Internet of things, Embedded, ASSP, BOM, MCU, Renesas Electronics, IGBT, IDE, Overalls, Architecture, Engineering, DAC, Completeness, Ecosystem, Business analyst, LLVM, Multimedia, ADC, Integrated development environment, CPU, Video game

Renesas Electronics Corporation (TSE:6723), a premier supplier of advanced semiconductor solutions, today announced the industry’s first general-purpose 32-bit RISC-V-based microcontrollers (MCUs) built with an internally developed CPU core.

Key Points: 
  • Renesas Electronics Corporation (TSE:6723), a premier supplier of advanced semiconductor solutions, today announced the industry’s first general-purpose 32-bit RISC-V-based microcontrollers (MCUs) built with an internally developed CPU core.
  • Similar to existing general-purpose MCUs, designers will have access to a full-scale development environment for the R9A02G021, provided by Renesas and its extensive network of toolchain partners.
  • The R9A02G021 group represents the first generation of general- purpose MCUs based on the internally developed RISC-V core by Renesas that will roll out over the next several years.
  • The R9A02G021 RISC-V MCUs are fully supported by Renesas’ e² studio Integrated Development Environment (IDE), offered to customers at no cost.

Global and China Automotive Memory Chip and Storage Industry Report 2024 Featuring 8 Global Chip Vendors and 20 Chinese Vendors - ResearchAndMarkets.com

Retrieved on: 
Tuesday, March 19, 2024
Technology, Vehicle Technology, Hardware, Automotive, Cloud, Socs, Flash memory, GPU, SerDes, LPDDR3, DDR5, BMS, ASP, JEDEC, Personal computer, EDR, PCB, FSD, NXP, PHY, UFS, HBM, SRAM, FRAM, Universal Flash Storage, BGA, DDR4, Electronics, LPDDR5, PCI Express, Memory, DDR, GDDR6, European, SK Hynix, EEPROM, NVM Express, Research, AI, CXL, IVI, Samsung, Compute Express Link, Cloud computing, Rambus, Micrometre, Intel, SOC, SSD, DRAM, MRAM, UFS 4.0, CPU, FPGA, IPS, TSMC, Video game

The "Global Automotive Memory Chip and Storage Industry Report, 2024" report has been added to ResearchAndMarkets.com's offering.

Key Points: 
  • The "Global Automotive Memory Chip and Storage Industry Report, 2024" report has been added to ResearchAndMarkets.com's offering.
  • The global automotive memory chip market was worth USD4.76 billion in 2023, and it is expected to reach USD10.25 billion in 2028 boosted by high-level autonomous driving.
  • Currently, among Tesla's automotive memory chips, the 2nd-generation FSD has the highest bandwidth ranging from 448Gb/s to 1008GB/s.
  • 4.2 Memory Chip Application Scenario: Autonomous Driving
    4.3 Memory Chip Application Scenario: Cockpit
    4.4 Application Scenario of Memory Chips: Central Computing Units + Zonal Controllers
    4.5 Memory Chip Application Scenario: Driving Data Recording
    4.6 Memory Chip Application Scenarios: Cloud Computing and Storage

Tachyum Demonstrates Machine Check and Recovery on Prodigy FPGA

Retrieved on: 
Tuesday, March 12, 2024
Technology, Hardware, Artificial Intelligence, Semiconductor, EDAC, Static, Prodigy, SRAM, CAPEX, OPEX, GPU, Memory, HPC, AI, Linux, Static random-access memory, Architecture, DDR, Universal, MCR, Economics, CPU, FPGA, Computer data storage

Tachyum ® today announced the addition of Machine Check and Recovery (MCR) capabilities with the Linux Error Detection and Correction (EDAC) subsystem to the Prodigy® Universal Processor with successful deployment demonstrated as part of the FPGA emulation system.

Key Points: 
  • Tachyum ® today announced the addition of Machine Check and Recovery (MCR) capabilities with the Linux Error Detection and Correction (EDAC) subsystem to the Prodigy® Universal Processor with successful deployment demonstrated as part of the FPGA emulation system.
  • When the degree of Static Random-Access Memory (SRAM) damage is beyond repair, the error detection allows affected computations to be abandoned rather than provide incorrect results.
  • Prodigy provides Double Error Correction and Triple Error Detection (DECTED), which is a key feature to improving uptime, and is complemented by EDAC to enable preventative maintenance.
  • By eliminating the need for expensive dedicated AI hardware and dramatically increasing server utilization, Prodigy reduces CAPEX and OPEX significantly while delivering unprecedented data center performance, power, and economics.

Demand for Real-time AI Inference from Groq® Accelerates Week Over Week

Retrieved on: 
Tuesday, April 2, 2024
Conservative Party (United States), HBM, SRAM, Government, GPU, Tensor, CUDA, Memory, Risk, Human, Running, AI, Software, Heat, Life, Carbon, Abstract, Architecture, Graphics processing unit, TAM, API, Economics, LPU, Plague, Video game

MOUNTAIN VIEW, Calif., April 2, 2024 /PRNewswire/ -- Groq®, a generative AI solutions company, announced today that more than 70,000 new developers are using GroqCloud™and more than 19,000 new applications are running on the LPU™ Inference Engine via the Groq API. The rapid migration to GroqCloud since its launch on March 1st indicates a clear demand for real-time inference as developers and companies seek lower latency and greater throughput for their generative and conversational AI applications.

Key Points: 
  • It's clear that developers are hungry for low-latency AI inference capabilities, and we're thrilled to see how it's being used to bring innovative ideas to life.
  • Today, ~40% of AI chips are leveraged for inference, and that alone would put the TAM for chips used for inference at ~$48B by 2027.
  • Once applications reach maturity they often allocate 90-95 percent of resources to inference, indicating a much larger market over time.
  • With nearly every industry and government worldwide looking to leverage generative and/or conversational AI, the TAM for AI chips, and systems dedicated to inference in particular, appears to be limitless.

Avalanche Technology Announces Two New Products in Its Upgradeable Small Form Factor Family of Gb STT-MRAM For Aerospace Applications

Retrieved on: 
Monday, March 25, 2024
Transfer, Temperature, SRAM, EEPROM, EAP, System, MRAM, Engineering, Life, RAM, Marketing, Low Earth orbit, STT-MRAM, GEO, Persistent, PDC, Parallel, FBGA, Video game

FREMONT, Calif., March 25, 2024 /PRNewswire-PRWeb/ -- Avalanche Technology, the leader in next generation MRAM technology, announced today two new densities of its 3rd generation space-grade parallel asynchronous x32-interface high-reliability P-SRAM (Persistent SRAM) memory devices, based on its latest Spin Transfer Torque Magneto-resistive RAM (STT-MRAM) technology.

Key Points: 
  • With this development, Avalanche Technology is leading an evolution toward a new level of performance versus cost for modern space electronic systems.
  • "We welcome the addition of Avalanche's higher densities in the same physical footprint.
  • With the new 8Gb P-SRAM device, customers can design unified memory architecture systems for high reliability aerospace applications, all in one small form factor."
  • All density options in Avalanche's Parallel x32 Space Grade series will be available to customers participating in the early access program.