CCIX

S2C's PCIe Gen5-Enabled S8-40 Prototyping System, Accelerating AI Design with High Performance

Retrieved on: 
Tuesday, July 4, 2023
Transfer, FMC, Data-rate units, CXL, AMD, DSP, Internet of things, S2C, CCIX, PAM4, Collection, Interlaken, SAN, HPC, EP, Prodigy, AI, Field-programmable gate array, Family, GPU, Video game, Sulfur, Computer data storage, Medical device, Printed circuit board, Satellite navigation device

Supporting high bandwidth connectivity including PCIe Gen5 and PAM4, S8-40 effectively addresses the verification needs of high bandwidth applications such as storage, AI, and GPU chip designs.

Key Points: 
  • Supporting high bandwidth connectivity including PCIe Gen5 and PAM4, S8-40 effectively addresses the verification needs of high bandwidth applications such as storage, AI, and GPU chip designs.
  • With the increasing adoption of AI, 5G, IoT, and autonomous driving, the demand for low real-time processing is growing more than ever.
  • These applications often require low-latency and high-bandwidth interfaces such as PCIe Gen5 and high-speed interconnect protocols such as CXL and CCIX.
  • Prodigy S8-40 is the first member of our 8th-generation prototyping solution to meet the verification requirements of AI and other bandwidth-intensive designs.

Riviera-PRO Supports System Simulation of AMD® Versal™ ACAP Designs

Retrieved on: 
Wednesday, June 14, 2023
Electronic Design Automation, Engineering, Technology, Manufacturing, Software, Hardware, HBM, PS, Programmable logic device, RTL, UVM, Network on a chip, PL, QEMU, Vitis, HDL, SOC, Marketing, CCIX, SystemC, DMA, ACAP, IPS, AIE, Algorithm, Artificial intelligence, Architecture, Transaction processing system, Environment, SystemVerilog, Video game, FPGA

Aldec, Inc. , a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and SoC designs, has unveiled the latest release of Riviera-PRO, providing support for system simulation of Versal™ Adaptive Compute Acceleration Platform (ACAP) designs.

Key Points: 
  • Aldec, Inc. , a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and SoC designs, has unveiled the latest release of Riviera-PRO, providing support for system simulation of Versal™ Adaptive Compute Acceleration Platform (ACAP) designs.
  • Riviera-PRO supports system simulation of Versal ACAP designs based on the Vitis™ hardware emulation flow for testing the interactions between AIE, PS, and PL.
  • System simulation is highly critical for any Versal ACAP design because of its complex adaptable architecture and high-logic density.
  • System simulation can be used to perform algorithmic validation, verify architectural extrapolation, connected hardware platforms and application software.

Avery Design Systems Announces SimXACT-SA(TM) for Improved Sequential X-Verification

Retrieved on: 
Tuesday, December 6, 2022
CXL, FlexRay, USB, SD, SAS, Gen-Z, SOC, CCIX, PCI Express, SATA, AHCI, NVM Express, HBM, MIPI, NVM, AMBA, UFS, FD, Computer data storage, Telescopic sight, MultiMediaCard

Tewksbury, Massachusetts--(Newsfile Corp. - December 6, 2022) - Avery Design Systems Inc., an innovator in functional IC verification productivity solutions, today announced the availability of a major new release to its patented SimXACT analysis solutions, adding features for sequential false X analysis and automatic repair and improved analysis and debug of clock gating logic.

Key Points: 
  • Tewksbury, Massachusetts--(Newsfile Corp. - December 6, 2022) - Avery Design Systems Inc., an innovator in functional IC verification productivity solutions, today announced the availability of a major new release to its patented SimXACT analysis solutions, adding features for sequential false X analysis and automatic repair and improved analysis and debug of clock gating logic.
  • The new release also improves overall runtime performance.
  • To view the full announcement, including downloadable images, bios, and more, click here .
  • The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers.

Avery Continues to Drive CXL Adoption with New Virtual Platform Features in Support of Version 3.0

Retrieved on: 
Tuesday, October 25, 2022
PCI Express, SOC, SATA, AMBA, CXL, Compute Express Link, NVM Express, Adoption, CCIX, SD, UFS, Gen-Z, SAS, FlexRay, Linux, Industry, USB, QEMU, NVM, MIPI, AHCI, FD, HBM, MultiMediaCard

Tewksbury, Massachusetts--(Newsfile Corp. - October 25, 2022) - Avery Design Systems, the leader in functional verification solutions, continues to drive the industry adoption of the Compute Express LinkTM (CXL) open industry-standard interconnect, introducing new features in its QEMU software virtual machine emulator based Linux host and SoC RTL co-simulation solution for system-level verification of complete CXL HW-SW systems.

Key Points: 
  • Tewksbury, Massachusetts--(Newsfile Corp. - October 25, 2022) - Avery Design Systems, the leader in functional verification solutions, continues to drive the industry adoption of the Compute Express LinkTM (CXL) open industry-standard interconnect, introducing new features in its QEMU software virtual machine emulator based Linux host and SoC RTL co-simulation solution for system-level verification of complete CXL HW-SW systems.
  • To view the full announcement, including downloadable images, bios, and more, click here .
  • The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers.
  • More information about the company may be found at www.avery-design.com .

Avery Announces 800G Ethernet VIP Virtual Network Co-Simulation Platform, Enabling SoC Pre-Silicon Validation in Real Networked Application Environments

Retrieved on: 
Tuesday, August 2, 2022
UFS, AMBA, FlexRay, CXL, AHCI, PCI Express, HBM, Gen-Z, SOC, NVM Express, Avery, CCIX, Ethernet, MIPI, USB, NVM, FD, SD, SATA, VIP, Communication, SAS, Internet service provider, Telescopic sight, Cryptocurrency, MultiMediaCard

Santa Clara, California--(Newsfile Corp. - August 2, 2022) - Avery Design Systems today announced that its fully-tested Verification IP (VIP) for 800Gbps Ethernet can now be used to perform virtual network co-simulation for the full layer Ethernet 2-7 network stack.

Key Points: 
  • Santa Clara, California--(Newsfile Corp. - August 2, 2022) - Avery Design Systems today announced that its fully-tested Verification IP (VIP) for 800Gbps Ethernet can now be used to perform virtual network co-simulation for the full layer Ethernet 2-7 network stack.
  • The combination of the VIP and a virtual co-simulation/co-emulation system enables the running of full hardware/software system verification on pre-silicon SoC RTL and software integrations.
  • System designers can now perform system-level validation of an SoC design's Ethernet and TCP/IP network interfaces using real network traffic workloads of communication, datacenter, and storage network protocols running on either host OS or virtual machine (guest OS) platforms.
  • Avery Design System's Ethernet VIP can now perform virtual network co-simulation for the full layer Ethernet 2-7 network stack.

Avery Design Systems PCI Express VIP Enables eTopus SerDes IP and Next-Generation ASIC and Chiplet Applications to Achieve Compliance and High-Speed Connectivity

Retrieved on: 
Tuesday, June 21, 2022
USB, HBM, NVM, PCI Express, SAS, SATA, FlexRay, SD, NVM Express, SerDes, Gen-Z, CCIX, CXL, MIPI, ASIC, IP, AHCI, FD, UFS, SOC, AMBA, Telescopic sight, MultiMediaCard, Multi-chip module

Tewksbury, Massachusetts--(Newsfile Corp. - June 21, 2022) - Avery Design Systems, a leader in functional verification solutions, today announced it has been chosen by eTopus as its verification IP solution partner for eTopus PCIe Gen 1-6 and 800G/400G Ethernet solutions and 112G SerDes IP for next-generation ASIC and Chiplet applications.

Key Points: 
  • Tewksbury, Massachusetts--(Newsfile Corp. - June 21, 2022) - Avery Design Systems, a leader in functional verification solutions, today announced it has been chosen by eTopus as its verification IP solution partner for eTopus PCIe Gen 1-6 and 800G/400G Ethernet solutions and 112G SerDes IP for next-generation ASIC and Chiplet applications.
  • To view the full announcement, including downloadable images, bios, and more, click here .
  • Click image above to view full announcement.
  • The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers.

Avery Design Systems Announces Verification Support for New UCIe Standard, Accelerating Adoption of Chiplet Interconnect Protocol

Retrieved on: 
Wednesday, June 15, 2022
USB, HBM, NVM, SAS, SATA, FlexRay, SD, NVM Express, Gen-Z, CCIX, CXL, MIPI, Avery, UCI, AHCI, FD, UFS, PCI Express, SOC, AMBA, Telescopic sight, MultiMediaCard

Tewksbury, Massachusetts--(Newsfile Corp. - June 15, 2022) - Avery Design Systems, a leader in functional verification solutions, today announced comprehensive support for the new UCIe (Universal Chiplet Interconnect Express) standard, providing an efficient approach to enable design and verification engineers to leverage the recently-introduced standard for die-to-die interface connectivity.

Key Points: 
  • Tewksbury, Massachusetts--(Newsfile Corp. - June 15, 2022) - Avery Design Systems, a leader in functional verification solutions, today announced comprehensive support for the new UCIe (Universal Chiplet Interconnect Express) standard, providing an efficient approach to enable design and verification engineers to leverage the recently-introduced standard for die-to-die interface connectivity.
  • Avery's offering includes high-quality models and test suites that support pre-silicon verification of systems using UCIe.
  • To view the full announcement, including downloadable images, bios, and more, click here .
  • The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers.

PCI Express VIP from Avery Design Systems Selected by Fungible for Ensuring Compliance, Connectivity in Hyperscale Data Centers

Retrieved on: 
Monday, February 28, 2022
Gen-Z, UFS, MIPI, SOC, FD, SAS, AMBA, DPU, NVM Express, SD, PCI Express, CXL, AHCI, Fungible Inc., FlexRay, HBM, IP, Compliance, SATA, NVM, Fungibility, CCIX, VIP, USB, Cryptocurrency, Telescopic sight, MultiMediaCard

Tewksbury, Massachusetts--(Newsfile Corp. - February 28, 2022) - Avery Design Systems, a leader in functional verification solutions, today announced its PCI Express Verification IP (VIP) has been selected by Fungible Inc., a data center infrastructure company, to ensure compliance and connectivity of its Fungible Data Processing Unit (DPU).

Key Points: 
  • Tewksbury, Massachusetts--(Newsfile Corp. - February 28, 2022) - Avery Design Systems, a leader in functional verification solutions, today announced its PCI Express Verification IP (VIP) has been selected by Fungible Inc., a data center infrastructure company, to ensure compliance and connectivity of its Fungible Data Processing Unit (DPU).
  • The Fungible DPU is an industry-first and addresses the most challenging requirements in hyperscale data centers running data-intensive applications and delivers radically improved performance and cost efficiencies.
  • To view the full announcement, including downloadable images, bios, and more, click here .
  • The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers.

Avery Design Systems Offers Comprehensive Verification Support for the New HBM3 Interface Standard

Retrieved on: 
Wednesday, December 8, 2021
NVM, HBM3, FlexRay, SAS, CAN, IP, PCI Express, Gen-Z, HBM, SOC, Rambus, UFS, Avery, CCIX, FD, NVM Express, MIPI, SD, SATA, AHCI, USB, AMBA, CXL, Video game console, Telescopic sight

Tewksbury, Massachusetts--(Newsfile Corp. - December 8, 2021) - Avery Design Systems, a leader in functional verification solutions, today announced comprehensive support for the new HBM3 interface standard.

Key Points: 
  • Tewksbury, Massachusetts--(Newsfile Corp. - December 8, 2021) - Avery Design Systems, a leader in functional verification solutions, today announced comprehensive support for the new HBM3 interface standard.
  • Rambus uses Avery's high-quality HBM3 memory models to verify the new Rambus HBM3 Memory Subsystem.
  • Customers can then license the Avery memory models for use in full SoC verification.
  • The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers.

PLDA Announces XpressLINK-SOC™ CXL Controller IP with Support for the AMBA CXS Issue B Protocol

Retrieved on: 
Tuesday, January 19, 2021
Networks, Semiconductor, Internet, Hardware, Technology, Computing, Acorn Computers, Peripheral Component Interconnect, Computer buses, Computer networking, Technology, PCI Express, Advanced Microcontroller Bus Architecture, ARM architecture, Computer network, CCIX, Arm Ltd.

PLDA, the industry leader in high-speed interconnect solutions, today announced that PLDAs industry-leading XpressLINK-SOC CXL IP provides full support for the AMBA CXS Issue B (CXS-B) interface protocol.

Key Points: 
  • PLDA, the industry leader in high-speed interconnect solutions, today announced that PLDAs industry-leading XpressLINK-SOC CXL IP provides full support for the AMBA CXS Issue B (CXS-B) interface protocol.
  • AMBA CXS is a credit-based streaming protocol that enables high-bandwidth transmission of packets between a user application and the protocol controller.
  • Using a CXS interface, the designer can bypass the controllers transaction layer, which can significantly reduce latency.
  • The CXS specification defines the interface between an on-chip interconnect, such as the Arm CoreLink Coherent Mesh Network, and a PCIe or CXL controller to optimize transport of CCIX and CXL packets.