Aldec Releases Automated Static Linting and CDC Analysis for Microchip FPGA and SoC FPGA Designs
The new release supports automatic conversion of Libero projects into ALINT-PRO’s environment for static linting and clock domain crossing (CDC) analysis of hardware designs in VHDL, Verilog or SystemVerilog.
- The new release supports automatic conversion of Libero projects into ALINT-PRO’s environment for static linting and clock domain crossing (CDC) analysis of hardware designs in VHDL, Verilog or SystemVerilog.
- CDC analysis is critical to designs with multiple asynchronous clocks and helps mitigate non-deterministic issues such as data incoherence as a result of metastability that inevitably appear in today’s large FPGA and SoC FPGA designs.
- “The use of advanced verification tools such as static linting and CDC analysis can significantly reduce the number of non-trivial bugs escaping into production, save engineering resource and more importantly, increase the reliability of FPGA and SoC FPGA designs,” said Louie De Luna, Director of Marketing at Aldec.
- “Designers using Libero SoC Design Suite can take advantage of Aldec’s ALINT-PRO to help detect functional errors earlier in the FPGA design cycle.”
In conjunction with the latest release of ALINT-PRO, Aldec and Microchip will be conducting a webinar that will be held on March 2, 2023 - Linting and CDC Analysis for Microchip FPGA Designs .