GDSII

The Double Digit Growth of the EDA (Electronic Design Automation) Market and How Magic2 Plans to Revolutionize the Process

Retrieved on: 
Monday, July 31, 2023
Zeta, GDSII, Magic, Senior, Marketing, Synthetic media, USB, GAAP, ESD Alliance, App Store (iOS/iPadOS), Patent, Risk, TSMC, Python, Keysight, News, Software, DFM, Epsilon, Electronics, EDA, Cadence, Circuit reliability, Suite, Automatic, Growth, Intellectual property, Voltage, API, IP, SOC, Silicon, Generative, GBT, PathWave Design, PPA, Family, OTC Markets Group, IC, HDL, MEMORY, HPC, SIP, EPS, AI, Cadence Design Systems, Inc. v. Avanti Corp, Security (finance), Video game, Printed circuit board, Management, Typesetting, Intermodal freight transport, Mobile phone, 3D printing, Semiconductor, RV, LVS, Delta, Synopsys, DRC, Allowance

From the News: Magic2, is an AI driven electronic design automation (EDA) software Suite helping engineers to speed up time consuming task work during the integrated circuits (IC) design phase.

Key Points: 
  • From the News: Magic2, is an AI driven electronic design automation (EDA) software Suite helping engineers to speed up time consuming task work during the integrated circuits (IC) design phase.
  • Magic2 consists of eight integrated software applications that each cover specific component processes of the IC design cycle.
  • The tools complement each other and will help drastically reduce the development costs and speed up the IC design development cycle.
  • So the race is on for creating IP in the EDA market and with a little " magic " it will keep growing.

Ausdia Introduces Spreadsheet Constraints at the 60th Design Automation Conference

Retrieved on: 
Friday, July 7, 2023
Electronic Design Automation, Semiconductor, Data Management, Technology, Software, Hardware, NXP Semiconductors, GDSII, RTL, Spreadsheet, Design Automation Conference, SOC, SDC, DFT, NXP, Conference, DAC, Audit

DESIGN AUTOMATION CONFERENCE – Ausdia , the leading developer of design constraints verification and management solutions, introduced a significant enhancement to its SDC platform at the 60th Design Automation Conference (DAC) 2023.

Key Points: 
  • DESIGN AUTOMATION CONFERENCE – Ausdia , the leading developer of design constraints verification and management solutions, introduced a significant enhancement to its SDC platform at the 60th Design Automation Conference (DAC) 2023.
  • Timevision SC allows constraint developers to both read and write timing constraints in a Spreadsheet format – typically ExcelTM.
  • Users can also export existing SDC to SC (Spreadsheet Constraints) format for simplified review and porting.
  • Ausdia is highlighting the Timevision platform in booth #2311 at the Design Automation Conference (DAC) at the San Francisco Moscone Convention Center, San Francisco, CA from July 10 - 12, 2023.

GBT Segmental Update: Magic2 a Suite of Eight AI Driven EDA Tools Assisting Engineers with Faster Semiconductor Design

Retrieved on: 
Tuesday, June 13, 2023
Zeta, DFM, Patent, IR, Epsilon, Voltage, Layout, EDA, USB, IC, Design, Ohm's law, Ageing, Software, Research, Circuit reliability, Temperature, ICS, Language, Delta, Suite, Flow to HDL, MEMORY, Risk, Automatic, OTC, Hardware, HDL, GBT, Open Artwork System Interchange Standard, Schematic, Family, News, Behavior, Printed circuit board, Typesetting, Transformer, Intermodal freight transport, RV, DRC, GDSII, LVS, Allowance

Magic2 (internal project name), is an AI driven electronic design automation (EDA) software Suite helping engineers to speed up time consuming task work during the integrated circuits (IC) design phase.

Key Points: 
  • Magic2 (internal project name), is an AI driven electronic design automation (EDA) software Suite helping engineers to speed up time consuming task work during the integrated circuits (IC) design phase.
  • This week GBT received patent approval for its Epsilon tool which means that four out of the eight tools received patent approval.
  • Magic2 consists of eight integrated software applications that each cover specific component processes of the IC design cycle.
  • The tools complement each other and will help drastically reduce the development costs and speed up the IC design development cycle.

Singapore-based Start-up SiNBLE Launches IC Design Implementation Service

Retrieved on: 
Thursday, May 25, 2023
Technology, Nanotechnology, Hardware, Semiconductor, Fin field-effect transistor, GDSII, RTL, HPC, ASIC, Mobile phone

Singapore-based start-up SiNBLE announced its official launch today, offering the integrated circuit (IC) and subsystem design implementation service.

Key Points: 
  • Singapore-based start-up SiNBLE announced its official launch today, offering the integrated circuit (IC) and subsystem design implementation service.
  • This service leverages abundant IC design experiences and resources to facilitate global fabless IC design companies, systems integrators, and ASIC providers to achieve short time-to-market and efficient resource allocation.
  • With a particular focus on FinFET nodes, SiNBLE is committed to simplifying IC design for its customers.
  • "We are excited to launch SiNBLE and offer a flexible IC design implementation service to the market," said Kevin Koh, CEO of SiNBLE.

Tessolve solidifies its Silicon Design solutions with the acquisition of P2fsemi, deepening its expertise in Physical Design

Retrieved on: 
Thursday, October 27, 2022
Semiconductor, Hardware, Electronic Design Automation, Technology, Software, R, Growth, Acquisition, Balaji, Wireless, Solution, Physical, Technology, Investment, Engineering, RTL, High-pass filter, ODM, ASIC, GDSII, CEO, Silicon, IPS, Management, Tessolve

Tessolve ( www.tessolve.com ), the semiconductor industry's leading engineering solution provider, has acquired Pico2Femto Semiconductor (P2fsemi), primarily focused on physical design solutions.

Key Points: 
  • Tessolve ( www.tessolve.com ), the semiconductor industry's leading engineering solution provider, has acquired Pico2Femto Semiconductor (P2fsemi), primarily focused on physical design solutions.
  • P2fsemi's acquisition significantly strengthens Tessolve's ASIC design offerings from RTL to GDSII signoff, with increased full-turnkey backend design expertise.
  • P2fsemi enables customers to get first-pass silicon success with their 100+ Physical Design experts specialized in technology nodes down to 3nm.
  • "P2fsemi team, with excellent Physical Design expertise in advanced process nodes, is a great addition to our strong engineering team delivering state-of-the-art Silicon Design solutions.

SFN Launches ‘Infrastructure Time Machine’ That Enables Fabs to Reduce Semiconductor Production Times 10 Fold and Increase Net Profit 40-50 Times

Retrieved on: 
Thursday, September 29, 2022
Semiconductor, Engineering, Technology, Manufacturing, 5G, Artificial Intelligence, ROI, Time, CMOS, Mechanics, ICS, Sale, Chip, Computer, GDSII, PMOS, Social media, ITMS, IOT, EVS, Synopsis, IP, Semiconductor fabrication plant, MOS, CEO, Technology, Samsung, POR, JMP, Logic, Silicon, PDK, IC, NMOS, ZTL, Summerland, SPICE, Multimedia, VHDL, LIB, Infographic, ITM, TSMC, SFN, Video game console, Semiconductor, Electronic component, Next, Cadence

Now, UK and other Western fabs can be competitive again, and even overtake the Taiwanese and Korean giants, while also securing best national interests and IP.

Key Points: 
  • Now, UK and other Western fabs can be competitive again, and even overtake the Taiwanese and Korean giants, while also securing best national interests and IP.
  • Bizen ZTL chips require far fewer processing layers, enabling complex devices to be manufactured in large-geometry fabs around the world.
  • This translates into a 40-50 fold increase in net profit for the Bizen-converted fab.
  • For more details about Bizen, ZTL and SFN, please visit https://www.wafertrain.com/blog , or join in the discussions at https://www.wafertrain.com/discussions , or on social media:

GBT Seeks to Develop an AI Empowered Technology for Automatic Compaction of Integrated Circuit Layout Data IPs

Retrieved on: 
Tuesday, February 15, 2022
EDA, GDSII, Silicon, Integrated circuit, IC, AI, Physics, Electronic, Public policy, Company, Forward-looking statement, U.S. Securities and Exchange Commission, Design, Solution, SAN, Security (finance), IOT, IP, Goal, RF, OTC, GLOBE, Technology, DFM, Deep learning, IPS, Software, Automation, Internet of things, Industry, GBT, Overalls, Research, ICS, GPS, Program, Artificial intelligence, Digital, Electronic design automation, Mobile phone, Analog, Blockchain

SAN DIEGO, Feb. 15, 2022 (GLOBE NEWSWIRE) -- GBT Technologies Inc. (OTC PINK: GTCH ) ("GBT” or the “Company”), is developing an AI empowered technology for automatic compaction of integrated circuit (IC) layout blocks. As modern ICs are ever growing in complexity and size there is a high demand for design automation to reduce silicon area and increase its yield. Microchips are expected to include more functionalities, consuming less power, reducing in size and ultimately cheaper. The semiconductor field is pushing the envelope by introducing smaller manufacturing processes scaling into deep nanometer ranges. Scaling down the manufacturing process enables billions of transistors on die, higher performance, and power consumption reduction, but introduces new design challenges due to complicated physics rules. IC projects may take longer time as they need to comply with a vast amount of complex design rules and constraints. It is the Company’s position that an automatic IC layout compaction technology can be an efficient way to reduce new and existing layout IPs size utilizing less silicon area with the goal of increasing the overall yield.

Key Points: 
  • SAN DIEGO, Feb. 15, 2022 (GLOBE NEWSWIRE) -- GBT Technologies Inc. ( OTC PINK:GTCH ) ("GBT or the Company), is developing an AI empowered technology for automatic compaction of integrated circuit (IC) layout blocks.
  • It is the Companys position that an automatic IC layout compaction technology can be an efficient way to reduce new and existing layout IPs size utilizing less silicon area with the goal of increasing the overall yield.
  • GBT is now designing an AI empowered technology to read existing and new microchips layout data with the goal of producing the densest layout block possible.
  • The technology is targeted for Analog, Digital, RF and MIXED integrated circuits styles with the goal of supporting GDSII and Oasis data.

Synopsys' Fusion Compiler Adopted by AMD

Retrieved on: 
Wednesday, February 19, 2020
Electronic design automation, Digital electronics, Electronic engineering, California, Advanced Micro Devices, Signoff, Epyc, Fusion, Synopsys, GDSII

Based on an evaluation process, the Fusion Compiler product delivered industry-leading performance, power and area (PPA) metrics.

Key Points: 
  • Based on an evaluation process, the Fusion Compiler product delivered industry-leading performance, power and area (PPA) metrics.
  • This work has additionally resulted in an expanded collaboration between Synopsys and AMD to optimize Synopsys applications on AMD EPYCprocessors, targeted to deliver marked runtime acceleration benefits when deploying the Fusion Compiler RTL-to-GDSII product across servers powered by AMD EPYC processors.
  • "Based on our evaluation results, Synopsys' Fusion Compiler helped us meet our performance and time-to-market goals for our latest products.
  • It provides Design Fusion, ECO Fusion, Signoff Fusion, and Test Fusion, resulting in the most predictable RTL-to-GDSII flow with the fewest iterations, as well as unsurpassed design frequency, power, and area.

Synopsys Unveils Fusion Compiler, Enabling 20 Percent Higher Quality-of-Results and 2X Faster Time-to-Results

Retrieved on: 
Tuesday, November 6, 2018
Electronic design, GDSII, Tape-out

This unified architecture shares technologies across the RTL-to-GDSII flow to enable a highly convergent system delivering 20 percent better QoR and 2X faster time-to-results (TTR).

Key Points: 
  • This unified architecture shares technologies across the RTL-to-GDSII flow to enable a highly convergent system delivering 20 percent better QoR and 2X faster time-to-results (TTR).
  • Fusion Compiler is tapeout-validated at market-leading semiconductor companies and has been proven to deliver the highest-quality designs.
  • Fusion Compiler also enables a single cockpit for RTL-to-GDSII implementation, enabling unparalleled levels of design productivity, flexibility, and throughput to maximize power, performance, and area (PPA) for the most challenging designs.
  • As a part of this effort, we evaluated adopting the new Fusion Compiler tool for SoC-based designs.