SystemVerilog

Accellera Announces IEEE 1800™-2023 Standard Available Through IEEE GET Program

Retrieved on: 
Monday, March 4, 2024

1800™-2023 Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language—is now available for download without charge, courtesy of Accellera as part of the IEEE GET Program.

Key Points: 
  • 1800™-2023 Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language—is now available for download without charge, courtesy of Accellera as part of the IEEE GET Program.
  • "Our close partnership with the IEEE Standards Association provides engineers with much needed standards fee-free,” stated Lu Dai, Accellera Chair.
  • To download the standard, visit the Accellera Downloads page/Available IEEE Standards .
  • For a list of Accellera and IEEE standards available for download at no cost, visit the Accellera Downloads page .

Accellera Systems Initiative Honors Shalom Bresticker with First Distinguished Service Award

Retrieved on: 
Tuesday, February 27, 2024

ELK GROVE, Calif., Feb. 27, 2024 (GLOBE NEWSWIRE) -- Accellera Systems Initiative (Accellera) announced today that Shalom Bresticker, a longtime friend and contributor to Accellera standards efforts, is honored with the first Distinguished Service Award.

Key Points: 
  • ELK GROVE, Calif., Feb. 27, 2024 (GLOBE NEWSWIRE) -- Accellera Systems Initiative (Accellera) announced today that Shalom Bresticker, a longtime friend and contributor to Accellera standards efforts, is honored with the first Distinguished Service Award.
  • Mr. Bresticker has been an electronics engineer for 30 years and more recently a technical editor for nearly a decade.
  • He was awarded the Accellera Technical Excellence Award in 2010 for his contributions to the Verilog, SystemVerilog, Verilog-AMS and OVL standards.
  • “Shalom has been an invaluable contributor to the development of Accellera standards,” stated Lu Dai, Accellera Chair.

Synopsys Launches Industry's First Complete 1.6T Ethernet IP Solution to Meet High Bandwidth Needs of AI and Hyperscale Data Center Chips

Retrieved on: 
Thursday, February 29, 2024

SUNNYVALE, Calif., Feb. 29, 2024 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) today delivered a dramatic increase in bandwidth and throughput for data-intensive AI workloads with the industry's first complete 1.6T Ethernet IP solution. Hyperscale data centers, a backbone in the era of pervasive intelligence, require high-bandwidth, low-latency chips and interfaces to process petabytes of data quickly. Synopsys' new 1.6T Ethernet IP solution enables design teams to create the industry's fastest chips for AI and data center networking applications.

Key Points: 
  • Synopsys' new 1.6T Ethernet IP solution enables design teams to create the industry's fastest chips for AI and data center networking applications.
  • Synopsys' comprehensive IP solution, including new 1.6T MAC and PCS Ethernet controllers, 224G Ethernet PHY IP , and verification IP, accelerates time to market for AI and HPC networking chips.
  • The complete 1.6T Ethernet IP solution optimizes hyperscale data center energy efficiency by reducing interconnect power consumption by up to 50% compared to existing SoC implementations.
  • The Synopsys 1.6T Ethernet solution, including all components – 1.6T MAC and PCS Controller IP, 224G PHY IP for advanced processes, and Verification IP for 1.6T Ethernet – are available now.

DVCon U.S. 2024 Advance Program Available

Retrieved on: 
Thursday, January 11, 2024

GAINESVILLE, Fla., Jan. 11, 2024 (GLOBE NEWSWIRE) -- The advance program is available for the 2024 Design and Verification Conference and Exhibition United States (DVCon U.S.), sponsored by Accellera Systems Initiative.

Key Points: 
  • GAINESVILLE, Fla., Jan. 11, 2024 (GLOBE NEWSWIRE) -- The advance program is available for the 2024 Design and Verification Conference and Exhibition United States (DVCon U.S.), sponsored by Accellera Systems Initiative.
  • DVCon U.S. will be held March 4-7 at the DoubleTree by Hilton Hotel in San Jose, California.
  • “DVCon continues to be the must-attend conference for the practicing design and verification engineer,” stated Tom Fitzpatrick, DVCon U.S. 2024 General Chair.
  • “The Steering Committee has worked hard to put together a wide-ranging program of technical presentations that offer something for everyone,” Fitzpatrick continued.

Riviera-PRO Supports System Simulation of AMD® Versal™ ACAP Designs

Retrieved on: 
Wednesday, June 14, 2023

Aldec, Inc. , a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and SoC designs, has unveiled the latest release of Riviera-PRO, providing support for system simulation of Versal™ Adaptive Compute Acceleration Platform (ACAP) designs.

Key Points: 
  • Aldec, Inc. , a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and SoC designs, has unveiled the latest release of Riviera-PRO, providing support for system simulation of Versal™ Adaptive Compute Acceleration Platform (ACAP) designs.
  • Riviera-PRO supports system simulation of Versal ACAP designs based on the Vitis™ hardware emulation flow for testing the interactions between AIE, PS, and PL.
  • System simulation is highly critical for any Versal ACAP design because of its complex adaptable architecture and high-logic density.
  • System simulation can be used to perform algorithmic validation, verify architectural extrapolation, connected hardware platforms and application software.

Verific Confirms Vorak as its Vendor of Choice for Providing Custom Development Services to Verific’s Customer Base

Retrieved on: 
Tuesday, May 2, 2023

“Vorak engineers are well-versed in Verific’s APIs,” remarks Rick Carlson, vice president of sales at Verific.

Key Points: 
  • “Vorak engineers are well-versed in Verific’s APIs,” remarks Rick Carlson, vice president of sales at Verific.
  • In one example, a floorplan estimator was developed for a Verific customer who needed block-level initial estimates.
  • “Verific is a company with a reputation of providing exceptional value and it’s a pleasure to work alongside its engineers,” says Georgi Mikichyan, COO of Vorak.
  • “Our projects implementing the Verific parser platforms or building on top of the platforms always reinforce that Verific’s reputation is well warranted.”

Accellera Systems Initiative Posthumously Honors Phil Moorby with 2023 Technical Excellence Award

Retrieved on: 
Wednesday, March 1, 2023

ELK GROVE, Calif., March 01, 2023 (GLOBE NEWSWIRE) -- Accellera Systems Initiative (Accellera) announced today that Phil Moorby, the inventor of the Verilog Hardware Description Language (HDL) who passed away in September 2022, is honored posthumously with the Accellera 2023 Technical Excellence Award.

Key Points: 
  • ELK GROVE, Calif., March 01, 2023 (GLOBE NEWSWIRE) -- Accellera Systems Initiative (Accellera) announced today that Phil Moorby, the inventor of the Verilog Hardware Description Language (HDL) who passed away in September 2022, is honored posthumously with the Accellera 2023 Technical Excellence Award.
  • The award was established to recognize the outstanding achievements of an individual and their significant contributions to the development of its standards.
  • He was honored with many awards for his work, including the prestigious Phil Kaufman Award in 2005.
  • “Phil Moorby invented and evolved the Verilog language, which has become the mainstay for the design of devices we all use every day,” stated Martin Barnasconi, Accellera Technical Committee Chair.

Aldec Releases Automated Static Linting and CDC Analysis for Microchip FPGA and SoC FPGA Designs

Retrieved on: 
Monday, February 6, 2023

The new release supports automatic conversion of Libero projects into ALINT-PRO’s environment for static linting and clock domain crossing (CDC) analysis of hardware designs in VHDL, Verilog or SystemVerilog.

Key Points: 
  • The new release supports automatic conversion of Libero projects into ALINT-PRO’s environment for static linting and clock domain crossing (CDC) analysis of hardware designs in VHDL, Verilog or SystemVerilog.
  • CDC analysis is critical to designs with multiple asynchronous clocks and helps mitigate non-deterministic issues such as data incoherence as a result of metastability that inevitably appear in today’s large FPGA and SoC FPGA designs.
  • “The use of advanced verification tools such as static linting and CDC analysis can significantly reduce the number of non-trivial bugs escaping into production, save engineering resource and more importantly, increase the reliability of FPGA and SoC FPGA designs,” said Louie De Luna, Director of Marketing at Aldec.
  • “Designers using Libero SoC Design Suite can take advantage of Aldec’s ALINT-PRO to help detect functional errors earlier in the FPGA design cycle.”
    In conjunction with the latest release of ALINT-PRO, Aldec and Microchip will be conducting a webinar that will be held on March 2, 2023 - Linting and CDC Analysis for Microchip FPGA Designs .

QuickLogic Drives eFPGA Innovation with New Aurora™ Development Tool Suite

Retrieved on: 
Tuesday, February 7, 2023

SAN JOSE, Calif., Feb. 7, 2023 /PRNewswire/ -- QuickLogic Corporation (NASDAQ: QUIK) has released a new version of its Aurora eFPGA development tool suite. The Aurora 2.1 Development Tool Suite is based on a fully open-source implementation for scalability, longevity, and full code transparency. It supports all major HDLs including Verilog, System Verilog, and VHDL.

Key Points: 
  • - Now supports all major Hardware Description Languages (HDL), including Verilog, System Verilog, and VHDL
    SAN JOSE, Calif., Feb. 7, 2023 /PRNewswire/ -- QuickLogic Corporation (NASDAQ: QUIK) has released a new version of its Aurora eFPGA development tool suite.
  • The Aurora 2.1 Development Tool Suite is based on a fully open-source implementation for scalability, longevity, and full code transparency.
  • It supports all major HDLs including Verilog, System Verilog, and VHDL.

GOWIN Semiconductor Partners with Metrics for Simulator Tool

Retrieved on: 
Wednesday, October 26, 2022

Metrics DSim Cloud is the first full feature, cloud-based simulator that supports SystemVerilog & VHDL design languages.

Key Points: 
  • Metrics DSim Cloud is the first full feature, cloud-based simulator that supports SystemVerilog & VHDL design languages.
  • Until now FPGA designers have been forced to make a very difficult tradeoff either use a very expensive simulator with great function and performance or choose an affordable simulator that isnt very good.
  • Metrics Dsim Cloud fills the gap, providing GOWIN with a simulator that has the function and performance of Cadence and Synopsys simulators but at an incredibly low price.
  • For more information about GOWIN, please visit www.gowinsemi.com
    Copyright 2022 GOWIN Semiconductor Corp. GOWIN, LittleBee, GW1N/NR/NS/1NSR/1NZ, Arora, GW2A/AR, GOWIN EDA and other designated brands included herein are trademarks of GOWIN Semiconductor Corp. in China and other countries.