Hardware verification languages

SmartDV Unveils Automation Tool Suite for Use with Its Extensive Verification IP Portfolio

Electronic design automation, Digital electronics, Electronic engineering, Hardware verification languages, Post-silicon validation, SystemC, Logic simulation

\xe2\x80\x9cIt is also time-consuming and typically requires detailed knowledge about the specific protocol being debugged.

Key Points: 
  • \xe2\x80\x9cIt is also time-consuming and typically requires detailed knowledge about the specific protocol being debugged.
  • That\xe2\x80\x99s why customers will find SmartDV\xe2\x80\x99s automation tool suite a welcome addition to our product portfolio.\xe2\x80\x9d\nSmartViP Debug works with all industry-standard waveform viewers and uses a profile-based architecture that supports all industry-standard protocols.
  • It supports multiple verification environments including simulation, emulation and SystemC.\nSmartTestBench automates the creation of testbench files to support a wide variety of verification scenarios.
  • With more than 600 products in its portfolio, SmartDV covers the design flow with Design IP and Verification IP for use in simulation, emulation, formal and post-silicon validation and memory models.

Cadence Pegasus Verification System Certified for Samsung Foundry 5nm and 7nm Process Technologies

Retrieved on: 
Monday, April 19, 2021
Electronic design automation, Semiconductor, Technology, Mobile, Wireless, Software, Hardware, Companies, Industry economics), Technology, Electronic design automation, Hardware verification languages, Semiconductor device fabrication, Signoff, 5 nm process, Cadence Design Systems, Samsung Electronics, Process design kit, Verification

b'Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that the Cadence\xc2\xae Pegasus\xe2\x84\xa2 Verification System has achieved certification for Samsung Foundry\xe2\x80\x99s 5nm and 7nm process technologies.

Key Points: 
  • b'Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that the Cadence\xc2\xae Pegasus\xe2\x84\xa2 Verification System has achieved certification for Samsung Foundry\xe2\x80\x99s 5nm and 7nm process technologies.
  • Samsung Foundry also delivered an enhanced, signoff-accurate process design kit (PDK) to facilitate the adoption of the Pegasus Verification System on the Samsung 5nm and 7nm technologies.\nThe Pegasus Verification System offers many advantages for engineers creating designs using Samsung\xe2\x80\x99s advanced nodes.
  • Additionally, the Pegasus Verification System features a tight, interactive integration with the Cadence Virtuoso\xc2\xae Layout Suite environment.
  • For more information on the Pegasus Verification System, please visit www.cadence.com/go/pegasusadvnd .\n\xe2\x80\x9cWe value our collaboration with Cadence and have worked diligently to enable our mutual customers to sign off their designs using the Pegasus Verification System and Samsung Foundry\xe2\x80\x99s advanced-node process technologies,\xe2\x80\x9d said Jong-Wook Kye, vice president of the Design Enablement Team at Samsung Electronics.

Foretellix Partners with Jingwei HiRain, to Accelerate the Use of its Automated Driving Systems Verification & Validation Platform in China

Retrieved on: 
Thursday, March 25, 2021
Pharmaceutical industry, Validity, Hardware verification languages, Verification, Electronic engineering, Validation, Health sciences, E, ADAS, Evaluation

Foretellix's novel verification platform Foretify, is already in use by leading OEM and Tier 1s such as DENSO Corporation.

Key Points: 
  • Foretellix's novel verification platform Foretify, is already in use by leading OEM and Tier 1s such as DENSO Corporation.
  • Foretifyuses coverage-driven verification tools and methodologies proven in the semiconductor chip industry to conduct the verification of software and hardware automated driving systems such as ADAS and AV stacks.
  • "With Foretellix's verification platform Foretifywe found an innovative and unique technology that perfectly complements our growing portfolio inthe automated driving systems verification area."
  • For more information, visit http://www.hirain.com
    Foretellix provides a revolutionary development lifecycle Verification & Validation platform for enabling mass deployment of automated driving systems.

Synopsys Announces Euclide to Accelerate Design and Verification Productivity

Retrieved on: 
Wednesday, March 3, 2021
Electronic engineering, Electronic design automation, Digital electronics, Hardware verification languages, Hardware description languages, Synopsys, SystemVerilog, E, Hardware description language, Universal Verification Methodology, Verilog, Verification

Synopsys, Inc. (Nasdaq: SNPS ) today introduced Synopsys Euclide , the industry's next-generation hardware description language (HDL)-awareintegrated development environment (IDE).

Key Points: 
  • Synopsys, Inc. (Nasdaq: SNPS ) today introduced Synopsys Euclide , the industry's next-generation hardware description language (HDL)-awareintegrated development environment (IDE).
  • Synopsys Euclide enables engineers to find bugs earlier and optimize code for design and verification flows by identifying complex design and testbench compliance checks during SystemVerilog and Universal Verification Methodology (UVM) development.
  • "The on-the-fly design and testbench checks in Synopsys Euclide have helped us in unmasking critical bugs otherwise identified at late design stages," said Assaf Shacham, Senior Hardware Engineering Manager at Microsoft Corporation.
  • "Synopsys Euclide is a unique, innovative and highly interactive code development platform that accelerates design and testbench development for VCS users."

UVM Reference Implementation Aligned with IEEE 1800.2-2020 Standard

Retrieved on: 
Wednesday, December 16, 2020
Hardware verification languages, Hardware description languages, Accellera, IEEE standards, IEEE Standards Association, E, University of Vermont, SystemVerilog, Electrical engineering, Electronic design automation, Universal Verification Methodology

The new reference implementation is aligned with the latest IEEE 1800.2-2020 Standard for UVM.

Key Points: 
  • The new reference implementation is aligned with the latest IEEE 1800.2-2020 Standard for UVM.
  • The IEEE standard is now available for download at no charge under the Accellera-sponsored IEEE Get Program.
  • "Our UVM Working Group has been very focused on aligning its UVM-2020 1.0 reference implementation with IEEE 1800.2-2020, giving users access to the latest enhancements in compliance with the new standard, stated Lu Dai, Accellera Chair.
  • Along with implementing these LRM updates, the new reference implementation addresses some errata that have existed in the UVM-1.2 implementation.

Verific and DARPA Sign Partnership for Streamlined Access to Industry-Standard SystemVerilog EDA Software

Retrieved on: 
Wednesday, December 16, 2020
Electronic engineering, Computer engineering, Integrated circuits, Electrical engineering, Hardware verification languages, SystemVerilog, DARPA, Electronic design automation, Integrated circuit design, Application-specific integrated circuit

ALAMEDA, Calif., Dec. 16, 2020 (GLOBE NEWSWIRE) -- Verific Design Automation today announced a partnership agreement with the U.S. Defense Advanced Research Projects Agency (DARPA) to provide the DARPA community access to its electronic design automation (EDA) software in production and development use throughout the semiconductor industry.

Key Points: 
  • ALAMEDA, Calif., Dec. 16, 2020 (GLOBE NEWSWIRE) -- Verific Design Automation today announced a partnership agreement with the U.S. Defense Advanced Research Projects Agency (DARPA) to provide the DARPA community access to its electronic design automation (EDA) software in production and development use throughout the semiconductor industry.
  • Our support of academic use over the years has been on an ad-hoc basis, remarks Michiel Ligthart, president and chief operating officer of Verific.
  • This agreement provides DARPA-funded programs easy and streamlined access to our industry-standard SystemVerilog parsers and elaborators, cracking open ways to meet DARPAs goal to innovate a fourth wave of electronics progress.
  • With offices in Alameda, Calif., and Kolkata, India, Verific has shipped more than 60,000 copies of its software used worldwide by the EDA and semiconductor industry since it was founded in 1999.

Draft of Accellera Portable Test and Stimulus Standard 2.0 Now Available for Public Review

Retrieved on: 
Wednesday, November 18, 2020
Accellera, Electronic engineering, Hardware description languages, Digital electronics, Hardware verification languages, Electronic design automation, IEEE standards

Accellera Systems Initiative, the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, announced the availability of the Portable Test and Stimulus Draft Standard 2.0 (PSS) for public review.

Key Points: 
  • Accellera Systems Initiative, the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, announced the availability of the Portable Test and Stimulus Draft Standard 2.0 (PSS) for public review.
  • The Portable Test and Stimulus Draft Standard 2.0 includes about 90% of the projected functionality that will be included in the official Portable Test and Stimulus Standard 2.0 release expected in March 2021.
  • Accelleras Portable Stimulus Working Group (PSWG) welcomes feedback from the community on the major additions included in the draft while the group finalizes the remaining functionality.
  • Accellera and Accellera Systems Initiative are trademarks of Accellera Systems Initiative Inc. All other trademarks and trade names are the property of their respective owners.

SmartDV Unveils SmartConf Testbench Generator

Electronic engineering, Electronic design automation, Hardware verification languages, Hardware description languages, Digital electronics, E, SystemVerilog, Verilog, SystemC, Intelligent verification, Aldec

SAN JOSE, Calif., Oct. 06, 2020 (GLOBE NEWSWIRE) -- SmartDV Technologies , the Proven and Trusted choice for Design and Verification intellectual property (IP), today unveiled SmartConf testbench generator, an add-on automation tool to its extensive Verification IP portfolio.

Key Points: 
  • SAN JOSE, Calif., Oct. 06, 2020 (GLOBE NEWSWIRE) -- SmartDV Technologies , the Proven and Trusted choice for Design and Verification intellectual property (IP), today unveiled SmartConf testbench generator, an add-on automation tool to its extensive Verification IP portfolio.
  • Handwritten testbenches are notoriously time consuming and error prone," remarks Deepak Kumar Tala, managing director of SmartDV.
  • Using SmartConf, verification engineers enter configuration inputs for a target testbench in a graphical user interface.
  • SmartConf generates testbenches in various industry standard languages and methodologies such as Verilog, SystemVerilog, SystemC and UVM with support for various SmartDV Verification IP.

Cadence Optimizes Digital Full Flow and Verification Suite for Arm Cortex-A78 and Cortex-X1 CPU Mobile Device Development

Retrieved on: 
Tuesday, May 26, 2020
Electronic design automation, Semiconductor, Technology, Telecommunications, Mobile, Wireless, Software, Hardware, Companies, Electronic engineering, Hardware verification languages, Fabless semiconductor companies, Cadence Design Systems, Digital electronics, ARM Holdings, Mentor Graphics, ARM Cortex-A, E

In addition, the Cadence Verification Suite and its engines have been optimized for the creation of Cortex-A78 and Cortex-X1 CPU-based designs, providing engineers with enhanced verification throughput.

Key Points: 
  • In addition, the Cadence Verification Suite and its engines have been optimized for the creation of Cortex-A78 and Cortex-X1 CPU-based designs, providing engineers with enhanced verification throughput.
  • The powerful combination of the Cadence Verification Suite and its engines have also been tuned and used to support Arm Cortex-A78 and Cortex-X1 CPU-based designs and augment verification throughput.
  • The Cadence Verification Suite is comprised of best-in-class core engines, verification fabric technologies and solutions that improve verification throughput.
  • Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc.

Philipp A. Hartmann to Receive Accellera Systems Initiative Technical Excellence Award

Retrieved on: 
Tuesday, February 25, 2020
Electronic engineering, Hardware description languages, Accellera, Digital electronics, Hardware verification languages, SystemC, Electronic design automation, IEEE standards, Universal Verification Methodology, High-level verification

ELK GROVE, Calif., Feb. 25, 2020 (GLOBE NEWSWIRE) -- Accellera Systems Initiative (Accellera) announced today that Philipp A. Hartmann, most recently Chair of the SystemC Language Working Group (LWG), is the recipient of the 2020 Accellera Technical Excellence Award.

Key Points: 
  • ELK GROVE, Calif., Feb. 25, 2020 (GLOBE NEWSWIRE) -- Accellera Systems Initiative (Accellera) announced today that Philipp A. Hartmann, most recently Chair of the SystemC Language Working Group (LWG), is the recipient of the 2020 Accellera Technical Excellence Award.
  • I am honored to receive this award from Accellera, said Hartmann.
  • DVCon is sponsored by Accellera Systems Initiative , an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies.
  • Accellera, Accellera Systems Initiative, and DVCon and are trademarks of Accellera Systems Initiative Inc. All other trademarks and trade names are the property of their respective owners.