Accellera

DVCon U.S. 2024 Announces Stuart Sutherland Best Paper & Best Poster Winners & Conference Highlights

Retrieved on: 
Tuesday, March 19, 2024
Shift, Infineon Technologies, Algorithm, Conference, Nvidia, UVM, Lens, PSS, Working Group, DoubleTree, Verification, Ford Motor Company, Human, Formal, Accellera, Functional, Texas Instruments, Exhibition, Paper, Cadence Design Systems, Poster, AMD, Automotive industry

The 2024 Best Paper and Poster winners, as voted on by attendees, were announced during a reception in the exhibit hall on March 6.

Key Points: 
  • The 2024 Best Paper and Poster winners, as voted on by attendees, were announced during a reception in the exhibit hall on March 6.
  • Overall attendance for DVCon U.S. 2024 was approximately 975, including attendees from 25 exhibiting companies.
  • “It was really an exciting time to be back at DVCon U.S.,” stated Tom Fitzpatrick, DVCon U.S. 2024 General Chair.
  • For the second consecutive year, the Poster Ninja Warrior Session determined the Stuart Sutherland Best Poster Award winners.

DVCon U.S. 2024 Announces Keynote Speakers & Panel Focused on Generative AI

Retrieved on: 
Thursday, February 15, 2024
Shift, Automotive industry, Siemens EDA, ARM, Ford Motor Company, FSS, PWG, Texas Instruments, Conference, Accellera, Best, Hilton Hotels & Resorts, Ford, Sasuke (TV series), DoubleTree, Chair, Working Group, Cadence Design Systems, Artificial intelligence, NVIDIA, Cryptocurrency

GAINESVILLE, Fla., Feb. 15, 2024 (GLOBE NEWSWIRE) -- The 2024 Design and Verification Conference and Exhibition United States (DVCon U.S.), sponsored by Accellera Systems Initiative, announced today that there will be two keynote speakers for attendees this year as well as a panel focused on generative Artificial Intelligence (AI).

Key Points: 
  • GAINESVILLE, Fla., Feb. 15, 2024 (GLOBE NEWSWIRE) -- The 2024 Design and Verification Conference and Exhibition United States (DVCon U.S.), sponsored by Accellera Systems Initiative, announced today that there will be two keynote speakers for attendees this year as well as a panel focused on generative Artificial Intelligence (AI).
  • DVCon U.S. 2024 will be held March 4-7 at the DoubleTree by Hilton Hotel in San Jose, California.
  • The first keynote, “ Addressing the Evolving Landscape of Automotive SoCs ,” will be held on Tuesday, March 5 at 1:30 pm.
  • ’” This panel invites participants to share and discuss their perspectives, experiences, insights, and apprehensions regarding the role of generative AI in verification.

Accellera Announces IEEE 1666™-2023 Standard Available Through IEEE GET Program

Retrieved on: 
Wednesday, November 8, 2023
Dai, IEEE Standards Association, LRM, Intellectual property, Digital twin, ISO C, Software, EDA, IEEE, Open, CIML community portal, SystemC, Partnership, Guaranteed Education Tuition Program, ELK, Electronics, Language, C, ISO, OSCI, Accellera

"Our close partnership with the IEEE Standards Association is a tremendous benefit to design and verification engineers around the globe,” stated Lu Dai, Accellera Chair.

Key Points: 
  • "Our close partnership with the IEEE Standards Association is a tremendous benefit to design and verification engineers around the globe,” stated Lu Dai, Accellera Chair.
  • It is a language built in standard C++ by extending the language with the use of class libraries.
  • As a partner in the GET Program since its inception, Accellera has sponsored more than 175,000 downloads of Accellera-developed standards.
  • For a list of Accellera and IEEE standards available for download at no cost, visit the Accellera Downloads page .

Accellera Releases Portable Test and Stimulus Standard 2.1

Retrieved on: 
Tuesday, October 10, 2023
Dai, Intellectual property, Accellera, PSS, Electronics, EDA, ELK, Portability testing, FPGA, 3D printing, Video game, Mobile phone, Computer data storage

“Industry adoption of the PSS standard continues to rise across the globe as new features are added to help increase productivity,” stated Lu Dai, Accellera Chair.

Key Points: 
  • “Industry adoption of the PSS standard continues to rise across the globe as new features are added to help increase productivity,” stated Lu Dai, Accellera Chair.
  • More Information and Background on Portable Stimulus:
    Accellera has resources available to learn more about portable stimulus and how it can positively impact your design and verification methodology.
  • Members of the working group presented a tutorial, “ User Experiences with the Portable Stimulus Standard ,” during DVCon U.S. 2023.
  • Feedback on the standard can also be provided through the Portable Stimulus Community Forum .

Accellera Announces Proposed Working Group to Explore Federated Simulation Standard

Retrieved on: 
Tuesday, August 22, 2023
Dai, Eclipse, Intellectual property, PWG, Eclipse Foundation, Electronics, AMD, EDA, FSS, API, AVL, IRT, Aptiv, Institute of Research and Technology b-com, Organization, Working Group, ELK, Airbus, Ecosystem, Cross-industry standard process for data mining, Research, NXP, 3D printing, Accellera, Qualcomm

ELK GROVE, Calif., Aug. 21, 2023 (GLOBE NEWSWIRE) -- Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, announced today the formation of a Federated Simulation Standard Proposed Working Group (PWG) to focus on the creation of a distributed and orchestrated multi-domain simulation framework.

Key Points: 
  • ELK GROVE, Calif., Aug. 21, 2023 (GLOBE NEWSWIRE) -- Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, announced today the formation of a Federated Simulation Standard Proposed Working Group (PWG) to focus on the creation of a distributed and orchestrated multi-domain simulation framework.
  • “A group of Accellera members have been part of a larger exploratory team looking at cross-industry collaboration to exchange knowledge and best practices,” stated Lu Dai, Chair of Accellera.
  • We look forward to the input from the industry during this initial standardization phase.”
    The first Proposed Working Group meeting will be held over two days in Toulouse, France.
  • Furthermore, the PWG will explore collaboration and partnerships with other organizations and communities to implement and prototype the standard API as part of the development of the federated simulation ecosystem.

DVCon U.S. 2023 Announces Stuart Sutherland Best Paper & Best Poster Winners

Retrieved on: 
Wednesday, March 8, 2023
Stuart Sutherland, Exhibition, Control, Portability testing, Paper, Beyond the Blue Horizon, Jet Propulsion Laboratory, DoubleTree, Algorithm, Electronics, NASA, IP, Verilog, Lunch, Poster, Intel, Microchip Technology, Renesas Electronics, Accellera, Steel, PSS, Ecosystem, Samsung, Siemens Digital Industries Software, Conference, PLL, Pharmaceutical industry, Video game, Nightclub, Synopsys

The 2023 Best Paper and Poster winners, as voted on by attendees, were announced during a reception in the exhibit hall on March 1.

Key Points: 
  • The 2023 Best Paper and Poster winners, as voted on by attendees, were announced during a reception in the exhibit hall on March 1.
  • “We were thrilled to be back in person this year,” stated Vanessa Cooper, DVCon U.S. 2023 General Chair.
  • "The energy and excitement from attendees was evident throughout the conference, especially during the new Poster Ninja Warrior Session.
  • The lunch concluded with Mark Himelstein, CTO of RISC-V International, giving a talk focused on “RISC-V Everywhere.”
    New to the program this year was the Poster Ninja Warrior Session to determine the Stuart Sutherland Best Poster Award winners.

Accellera Systems Initiative Posthumously Honors Phil Moorby with 2023 Technical Excellence Award

Retrieved on: 
Wednesday, March 1, 2023
Helmholtz International Fellow Award, ELK, SystemVerilog, Mathematics, Computer History Museum, HDL, Accellera, Computer, Verilog, University of Manchester, Film industry

ELK GROVE, Calif., March 01, 2023 (GLOBE NEWSWIRE) -- Accellera Systems Initiative (Accellera) announced today that Phil Moorby, the inventor of the Verilog Hardware Description Language (HDL) who passed away in September 2022, is honored posthumously with the Accellera 2023 Technical Excellence Award.

Key Points: 
  • ELK GROVE, Calif., March 01, 2023 (GLOBE NEWSWIRE) -- Accellera Systems Initiative (Accellera) announced today that Phil Moorby, the inventor of the Verilog Hardware Description Language (HDL) who passed away in September 2022, is honored posthumously with the Accellera 2023 Technical Excellence Award.
  • The award was established to recognize the outstanding achievements of an individual and their significant contributions to the development of its standards.
  • He was honored with many awards for his work, including the prestigious Phil Kaufman Award in 2005.
  • “Phil Moorby invented and evolved the Verilog language, which has become the mainstay for the design of devices we all use every day,” stated Martin Barnasconi, Accellera Technical Committee Chair.

DVCon U.S. 2023 Announces Keynote Speaker

Retrieved on: 
Wednesday, February 8, 2023
CHIPS, Farm, Algorithm, Hilton Hotels & Resorts, Sasuke (TV series), DoubleTree, Research, Conference, SEMI, Verification, Accellera, Steel, Lobster, Video game

GAINESVILLE, Fla., Feb. 08, 2023 (GLOBE NEWSWIRE) -- The 2023 Design and Verification Conference and Exhibition United States (DVCon U.S.), sponsored by Accellera Systems Initiative, announced today that Dirk Didascalou, Chief Technology Officer, Siemens Digital Industries, will be the keynote speaker for this year’s conference.

Key Points: 
  • GAINESVILLE, Fla., Feb. 08, 2023 (GLOBE NEWSWIRE) -- The 2023 Design and Verification Conference and Exhibition United States (DVCon U.S.), sponsored by Accellera Systems Initiative, announced today that Dirk Didascalou, Chief Technology Officer, Siemens Digital Industries, will be the keynote speaker for this year’s conference.
  • The in-person event will be held February 27-March 2, 2023 at the DoubleTree by Hilton Hotel in San Jose, California.
  • Mr. Didascalou will present, “ What Do Farming, Steel, and Space Have in Common ?” on Tuesday, February 28 from 1:30-2:30pm in the Oak/Fir Ballroom.
  • In addition to the two panels and keynote, including the Accellera-sponsored sessions, there will be 41 paper presentations, 17 poster sessions, four tutorials and 16 workshops throughout the four-day program.

Accellera’s Security Annotation for Electronic Design Integration Standard 1.0 Moves Toward IEEE Standardization

Retrieved on: 
Tuesday, January 17, 2023
Dai, IEEE, SA, Working Group, IPSA, Silicon, Partnership, Intellectual property, Electronics, ELK, IP, EDA, Electronic, Mobile phone, Accellera

ELK GROVE, Calif., Jan. 17, 2023 (GLOBE NEWSWIRE) -- Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, announced today that its Security Annotation for Electronic Design Integration (SA-EDI) Standard 1.0 has been contributed to the IEEE for the development of the P3164 draft standard.

Key Points: 
  • ELK GROVE, Calif., Jan. 17, 2023 (GLOBE NEWSWIRE) -- Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, announced today that its Security Annotation for Electronic Design Integration (SA-EDI) Standard 1.0 has been contributed to the IEEE for the development of the P3164 draft standard.
  • The IEEE P3164 Working Group will be established at the kick-off meeting on February 14 and will drive the ongoing progression of the SA-EDI standard.
  • Developed by Accellera’s IP Security Assurance (IPSA) Working Group, SA-EDI 1.0 defines a specification that documents security concerns for hardware IP and its associated components when integrated into an integrated circuit (IC).
  • To learn more about the SA-EDI Standard and how it can help IP providers identify security concerns, there are resources on Accellera’s IP Security Assurance Working Group page as well as the IEEE Security Annotation for Electronic Design Integration page .

Accellera Announces the Formation of the Clock Domain Crossing Working Group

Retrieved on: 
Tuesday, January 17, 2023
Dai, WG, Ecosystem, Clock domain crossing, Working Group, Environment, Intellectual property, Electronics, ELK, Electron capture, LRM, IP, Pahari language, CDC, EDA, Accellera, SOC

ELK GROVE, Calif., Jan. 17, 2023 (GLOBE NEWSWIRE) -- Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, announced today the formation of the Clock Domain Crossing (CDC) Working Group (WG).

Key Points: 
  • ELK GROVE, Calif., Jan. 17, 2023 (GLOBE NEWSWIRE) -- Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, announced today the formation of the Clock Domain Crossing (CDC) Working Group (WG).
  • The charter of the new working group is to define a standard CDC collateral specification to ease SoC integration.
  • “Our newest working group will address the current incompatibility of collateral generated by different CDC verification tools, which will help to greatly improve productivity.
  • If you are not already an Accellera member and are interested in joining to participate in the working group and the ongoing development of the standard, visit here