Join Andes at RISC-V Summit; Learn the Only ISO 26262 Fully-Compliant RISC-V CPU, the Latest Multicore 4-Way Out-Of-Order Processor & the Multicore 1024-bit Vector Processor
The company will contribute three presentations and will also demonstrate its cutting-edge RISC-V CPU IP solutions at booth #D4.
- The company will contribute three presentations and will also demonstrate its cutting-edge RISC-V CPU IP solutions at booth #D4.
- Furthermore, Hubert Chung, FAE Manager of Andes Technology, will give a talk on “Andes AI solutions: AndesClarity and NN/Vector Libraries” on December 14 at 1:00 PM at Demo Theater.
- In these informative speeches, the audience will get to learn the leading AndesCore™ RISC-V processor IP solutions.
- Besides presentations and live demo, Andes will join the RISC-V Member Day which kicks off the whole event on December 12.