Instruction set architectures

NSITEXE Successfully Develops Multiple Custom Processors for Automotive Applications in Half the Time with Synopsys ASIP Designer Tool

Retrieved on: 
Thursday, September 17, 2020
Computer engineering, Computing, Digital electronics, Instruction set architectures, Arc, System on a chip, Synopsys, Multi-core processor, Semiconductor intellectual property core, ASIP, Application-specific instruction set processor

Synopsys, Inc. (Nasdaq: SNPS )today announced that NSITEXE, a group company of DENSO Corporation that develops and sells high-performance semiconductor IP, used the Synopsys ASIP Designer Tool in the development of five specialized custom processors, including dedicated vector-processing engines, for its automotive data flow processor (DFP) platform.

Key Points: 
  • Synopsys, Inc. (Nasdaq: SNPS )today announced that NSITEXE, a group company of DENSO Corporation that develops and sells high-performance semiconductor IP, used the Synopsys ASIP Designer Tool in the development of five specialized custom processors, including dedicated vector-processing engines, for its automotive data flow processor (DFP) platform.
  • With ASIP Designer, NSITEXE was able to optimize the processors' multicore architecture and automatically generate software development kits (SDKs), enabling the company to design the custom processors in half the time compared to designing them from scratch.
  • ASIP Designer enabled us to develop the data flow processor model in record time and deliver it to the customer on schedule."
  • "Innovative companies like NSITEXE have adopted ASIP Designer to speed the development of their custom processors," said John Koeter, senior vice president of marketing and strategy for IP at Synopsys.

SiFive To Introduce New RISC-V Processor Architecture and RISC-V PC at Linley Fall Virtual Processor Conference

Retrieved on: 
Monday, September 14, 2020
Semiconductor, Hardware, Data management, Technology, Software, Computer architecture, Fabless semiconductor companies, Instruction set architectures, Microprocessors, SiFive, Computing, RISC-V, Arc

SiFive, Inc., the leading provider of commercial RISC-V processor IP and silicon solutions, today announced that Dr. Yunsup Lee, CTO of SiFive, and Dr. Krste Asanovic, Chief Architect of SiFive, will present at the technology industrys premier processor conference, the Linley Fall Virtual Processor Conference.

Key Points: 
  • SiFive, Inc., the leading provider of commercial RISC-V processor IP and silicon solutions, today announced that Dr. Yunsup Lee, CTO of SiFive, and Dr. Krste Asanovic, Chief Architect of SiFive, will present at the technology industrys premier processor conference, the Linley Fall Virtual Processor Conference.
  • This year's Linley Fall Processor Conference will feature our biggest program yet and will introduce a host of new technology disclosures and product announcements of innovative processor architectures and IP technologies," said Linley Gwennap, principal analyst and conference chairperson.
  • Designed for scalability, SiFive Core IP can be tailored to workload requirements through the highly-configurable parameters of the architecture.
  • Registration for The Linley Group Fall Virtual Processor Conference is free and open now for qualified registrants.

SiFive and Barcelona Supercomputing Center Advance Industry Adoption of RISC-V Vector Extension

Retrieved on: 
Thursday, September 3, 2020
Technology, Semiconductor, Security, Other Technology, Software, Networks, Hardware, Electronic design automation, Data management, Computer architecture, Computing, Microprocessors, Instruction set architectures, Fabless semiconductor companies, SiFive, Classes of computers, Parallel computing, RISC-V, Chris Lattner, Reduced instruction set computer, LLVM

In collaboration with the Barcelona Supercomputing Center, SiFive created an API for vector intrinsics for popular open-source compilers GCC, and LLVM.

Key Points: 
  • In collaboration with the Barcelona Supercomputing Center, SiFive created an API for vector intrinsics for popular open-source compilers GCC, and LLVM.
  • Additionally, SiFive reports that the SiFive Shield Hardware Cryptographic Accelerator (HCA) true random number generator (TRNG) has successfully passed conformance evaluation to SP 800-90B standard, to enable FIPS 140 certified security solutions.
  • The new API will speed up the development of vector processor applications using RISC-V processor cores with RISC-V Vector Extension (RVV) 1.0 support, such as the upcoming SiFive Intelligence line of products.
  • The RISC-V Vector extension will enable new RISC-V based processor designs to accelerate many workloads, from AI to signal processing and scientific research, said Chris Lattner, President of Platform Engineering, SiFive.

Synopsys and Nestwave Collaborate to Develop a Low-Power Geolocation IP Solution for IoT Modems

Retrieved on: 
Thursday, September 3, 2020
Computing, Computer architecture, Instruction set architectures, Microprocessors, Embedded microprocessors, Ambient intelligence, Digital technology, Internet of things, Arc, Ceva, ARM Holdings

"Today's advanced navigation systems are facing unique challenges when being implemented in power-constrained IoT devices," said Ambroise Popper, CEO at Nestwave.

Key Points: 
  • "Today's advanced navigation systems are facing unique challenges when being implemented in power-constrained IoT devices," said Ambroise Popper, CEO at Nestwave.
  • "By combining Nestwave's low power geolocation software with Synopsys' efficient ARC IoT Communications IP Subsystem, we can deliver a geolocation solution that offers greater accuracy, lower power consumption, and lower cost compared to existing GNSS solutions."
  • The ARC IoT Communications IP Subsystem is an integrated hardware and software solution that combines Synopsys' DSP-enhanced ARC EM9D processor, hardware accelerators, dedicated peripherals, and RF interface to deliver efficient DSP performance for ultra-low bandwidth IoT applications.
  • To accelerate prototyping, software development and integration of IP into SoCs, Synopsys' IP Accelerated initiative offers IP prototyping kits, IP software development kits and IP subsystems.

Synopsys and Nestwave Collaborate to Develop a Low-Power Geolocation IP Solution for IoT Modems

Retrieved on: 
Thursday, September 3, 2020
Computing, Computer architecture, Instruction set architectures, Microprocessors, Embedded microprocessors, Ambient intelligence, Digital technology, Internet of things, Arc, Ceva, ARM Holdings

"Today's advanced navigation systems are facing unique challenges when being implemented in power-constrained IoT devices," said Ambroise Popper, CEO at Nestwave.

Key Points: 
  • "Today's advanced navigation systems are facing unique challenges when being implemented in power-constrained IoT devices," said Ambroise Popper, CEO at Nestwave.
  • "By combining Nestwave's low power geolocation software with Synopsys' efficient ARC IoT Communications IP Subsystem, we can deliver a geolocation solution that offers greater accuracy, lower power consumption, and lower cost compared to existing GNSS solutions."
  • The ARC IoT Communications IP Subsystem is an integrated hardware and software solution that combines Synopsys' DSP-enhanced ARC EM9D processor, hardware accelerators, dedicated peripherals, and RF interface to deliver efficient DSP performance for ultra-low bandwidth IoT applications.
  • To accelerate prototyping, software development and integration of IP into SoCs, Synopsys' IP Accelerated initiative offers IP prototyping kits, IP software development kits and IP subsystems.

Tachyum Shows Prodigy Running Existing x86, ARM, and RISC-V Software

Retrieved on: 
Tuesday, August 4, 2020
Data management, Technology, Other Technology, Telecommunications, Software, Hardware, Computer architecture, Instruction set architectures, Computing, Computers, RISC-V, ARM architecture, Reduced instruction set computer, x86, Emulator, Binary translation, QEMU

Tachyum Inc. today announced that its Prodigy Universal Processor has successfully completed software emulation testing across x86, ARM and RISC-V binary environments.

Key Points: 
  • Tachyum Inc. today announced that its Prodigy Universal Processor has successfully completed software emulation testing across x86, ARM and RISC-V binary environments.
  • The emulation is to smoothly transition to native software for Tachyum Prodigy.
  • Tachyum is working on native Linux distribution with many applications in time for the Prodigy launch in 2021.
  • Despite software emulation on the Prodigy chip, the ARM and RISC-V binaries will run much faster on Tachyum Prodigy than on ARM or RISC-V available today.

Curvature announced as official Data Center Solutions Premium Support Partner for Intel® Server Maintenance globally

Retrieved on: 
Thursday, July 30, 2020
Companies, Computing, Intel, Xeon, Industries, Instruction set architectures, ThinkServer, Intel Active Management Technology

"To achieve this partnership with Intel Corporation, Curvature has demonstrated and qualified expertise on Intel server products to the highest standards," noted Joel Shehadi, Regional VP, Sales, Curvature.

Key Points: 
  • "To achieve this partnership with Intel Corporation, Curvature has demonstrated and qualified expertise on Intel server products to the highest standards," noted Joel Shehadi, Regional VP, Sales, Curvature.
  • "In doing so, we spent many months developing premium support capabilities specifically for Intel environments culminating in a 12-month pilot across Australia.
  • As one of just a handful of global vendors selected, being a recognized Intel Data Center Solutions Premier Support Partner means that Curvature can now offer direct support from its over 100 service centers globally using Curvature trained (and Intel accredited) engineers.
  • Intel Server Support provided by Curvature today includes Intel Xeon Scalable Processor including S2600BP, S2600WF, S2600ST product families; 2nd Generation Intel Xeon Scalable Processor including S2600BPR, S2600WFR, S2600STR product families; Intel Server System S9200WK product family.

Global SRAM and ROM Design IP Market - Growth, Trends, and Forecasts (2020 - 2025)

Retrieved on: 
Thursday, July 23, 2020
Computer engineering, Computing, Computer architecture, Instruction set architectures, Embedded microprocessors, Field-programmable gate array, Hardware acceleration, Microcontroller, Ice, SuperH

The board is based upon Lattice iCE40UP5k FPGA, with 4Mb qSPI flash and 64Mb qSPI SRAM.

Key Points: 
  • The board is based upon Lattice iCE40UP5k FPGA, with 4Mb qSPI flash and 64Mb qSPI SRAM.
  • - However, the growing advancement in the EEPROM segment, especially in 2019, and emerging various new applications for microcontrollers, are some of the significant factors providing support to the ROM design IP market.
  • TSMC has formed alliances and partnerships with various design and IP providers; also, the company is increasingly focusing on reducing its dependence on design IP vendors.
  • For example, TSMS and Synopsys have formed an alliance to develop a portfolio of design IP for various memory solutions
    The global SRAM and ROM Design IP market are moderately fragmented.

OneSpin Solutions to Participate at the 57th Design Automation Conference Highlighting Certified IC Integrity Verification Solutions in the Technical Program

Retrieved on: 
Wednesday, July 15, 2020
Technology, Semiconductor, Automotive, General Automotive, Automotive Manufacturing, Telecommunications, Software, Manufacturing, Hardware, Electronic design automation, Digital technology, Instruction set architectures, Microcontrollers, Electronic engineering, RISC-V, Formal verification, Computing, Integrated circuit

OneSpin Solutions , provider of certified IC integrity verification solutions for building functionally correct, safe, secure and trusted integrated circuits will have a visible presence at the upcoming Design Automation Conference , being held virtually July 20 24, 2020.

Key Points: 
  • OneSpin Solutions , provider of certified IC integrity verification solutions for building functionally correct, safe, secure and trusted integrated circuits will have a visible presence at the upcoming Design Automation Conference , being held virtually July 20 24, 2020.
  • OneSpin will present its RISC-V Integrity Verification Solution and share the results of formal verification of RISC-V cores and SoCs.
  • OneSpin Solutions is a leading provider of certified IC integrity verification solutions for building functionally correct, safe, secure and trusted integrated circuits.
  • OneSpin, OneSpin Solutions and the OneSpin logo are trademarks of OneSpin Solutions GmbH.

Synopsys and Arm Extend Strategic Partnership to Deliver Superior Full-Flow Quality-of-Results and Time-to-Results

Retrieved on: 
Monday, June 29, 2020
Acorn Computers, Computer architecture, Companies, Fabless semiconductor companies, Hillsboro, Oregon, Synopsys, Instruction set architectures, ARM Holdings, ARM architecture, Computers

With this agreement, Synopsys and Arm will jointly develop and distribute optimized Synopsys product reference methodologies to Arm customers and deliver training on the use of Synopsys products and flows with ArmIP.

Key Points: 
  • With this agreement, Synopsys and Arm will jointly develop and distribute optimized Synopsys product reference methodologies to Arm customers and deliver training on the use of Synopsys products and flows with ArmIP.
  • Synopsys' early access to Arm pre-production IP ensures that early licensees of the latest Arm cores have optimized products and methodology in place before they begin their design projects.
  • "Our strategic collaboration with Synopsys over the last three decades enables our mutual customers to implement high-performance and energy-efficient Arm-based SoCs," saidCiaran Dunne, vice president and general manager, Partner Enablement Groupat Arm.
  • Under the agreement, Synopsys receives early access to ArmCortexand Arm Neoverse processors, Arm MaliGPUs, Arm CoreLinksystem IP, Arm Artisanphysical IP, Arm Mali image signal processors and Arm POPIP.