Instruction set architectures

Telink and Andes Announce the TLSR9 SoC with RISC-V Processor

Retrieved on: 
Monday, November 2, 2020

SANTA CLARA, Calif., Nov. 2, 2020 /PRNewswire-PRWeb/ --Telink Semiconductor and Andes Technology are proud to introduce the new connectivity system on a chip (SoC) for Telink's latest product line, the TLSR9 series.

Key Points: 
  • SANTA CLARA, Calif., Nov. 2, 2020 /PRNewswire-PRWeb/ --Telink Semiconductor and Andes Technology are proud to introduce the new connectivity system on a chip (SoC) for Telink's latest product line, the TLSR9 series.
  • The Telink TLSR9 series is the latest addition to Telink's line of complete connectivity solutions, and it is designed to maximize device performance and minimize time to market.
  • The TLSR9 series is designed using the AndeStar V5 Instruction Set Architecture (ISA), which complies with the latest RISC-V technology.
  • The TLSR9 SoC features the D25F RISC-V processor, and is the world's first SoC that adopts a RISC-V DSP/SIMD P-extension, which is ideal for a variety of mainstream audio, wearables, and IoT development needs.

Renesas Extends RA MCU Family with RA6T1 MCU Group for Motor Control and AI-based Endpoint Predictive Maintenance

Retrieved on: 
Wednesday, October 28, 2020

The RA6T1 MCUs combine the superior performance and flexibility of the Arm-based RA Family with Renesas long-standing motor control expertise.

Key Points: 
  • The RA6T1 MCUs combine the superior performance and flexibility of the Arm-based RA Family with Renesas long-standing motor control expertise.
  • In addition, with the emergence of AI-based needs, Renesas is excited to complement Googles TensorFlow Lite supported platforms with the RA6T1 motor control and predictive maintenance solution.
  • Integrating our open-source TensorFlow AI framework with Renesas powerful RA6T1 MCUs brings breakthrough intelligence to motor control equipment.
  • Renesas will also continue to expand its RA Partner Network to include collaboration with leading companies in the motor control field.

Truechip Adds New Customer Shipments Of Verification IPS For RISC-V Family Including Tilelink

Retrieved on: 
Tuesday, October 27, 2020

NOIDA and BENGALURU, India, Oct. 27, 2020 /PRNewswire/ -- Truechip , the Verification IP Specialist, today announced that it has added multiple new customers for its RISC-V Verification IPs including TileLink .

Key Points: 
  • NOIDA and BENGALURU, India, Oct. 27, 2020 /PRNewswire/ -- Truechip , the Verification IP Specialist, today announced that it has added multiple new customers for its RISC-V Verification IPs including TileLink .
  • On this occasion, Nitin Kishore , CEO, Truechip, said, "I am pleased to announce that we have added multiple new customer shipments of our RISC-V family of Verification IPs.
  • Mr. Kishore further added, "In addition to other RISC-V related VIPs, I would like to give a special mention about our TileLink VIP.
  • It supports all channels including the TL-C and we support full cache coherency with checks, tests and cache models.

Renesas Shifts Mobility System Development Into High Gear With Its New Online Market Place for R-Car SoC

Retrieved on: 
Tuesday, October 27, 2020

Developers can download various solutions designed for Renesas R-Car automotive system-on-chips (SoCs) directly from the Market Place.

Key Points: 
  • Developers can download various solutions designed for Renesas R-Car automotive system-on-chips (SoCs) directly from the Market Place.
  • View the full release here: https://www.businesswire.com/news/home/20201027005403/en/
    Renesas shifts mobility system development into high gear with its online Market Place for R-Car SoC (Graphic: Business Wire)
    Through the Market Place, developers can quickly and easily access R-Car evaluation software, documentation such as hardware manuals, technical updates, application notes, and basic software such as Linux and Android board support packages (BSPs).
  • Designed to boost the efficiency of mobility system development, the Market Place will contribute to reducing the time required for development and jump start evaluation projects using R-Car Starter Kits .
  • The R-Car Consortium was established by Renesas in 2005 as a customer-oriented ecosystem that provides an open platform for the mobility market.

Attend Andes Technology Principal Engineer, Thang Tran’s, Presentation "A RISC-V Out-of-Order Processor" at the Linley Processor Conference Wednesday October 21st at 9:30 AM

Retrieved on: 
Monday, October 12, 2020

"The AI processor market will expand..., hitting $68.5 billion by the mid-2020s, IHS Markit predicts.

Key Points: 
  • "The AI processor market will expand..., hitting $68.5 billion by the mid-2020s, IHS Markit predicts.
  • AI is already propelling massive demand growth for microchips, said Luca De Ambroggi, senior research director for AI at IHS Markit .
  • Andes Technology is the first offer a RISC-V vector processor core that provides the performance being demanded by these emerging applications.
  • Andes Technology's comprehensive RISC-V CPU families range from the entry-level 32-bit N22, mid-range 32-bit N25F/D25F/A25/A27and 64-bit NX25F/AX25/AX27, to the high-end multicore A(X)25MPand vector processor NX27V.

Arm and RISC-V Software Development Solution from Ashling: RiscFree™ for Arm & RISC-V

Retrieved on: 
Thursday, October 8, 2020

Ashling, a leading provider of embedded development tools, has today announced advanced support for heterogeneous multi-core Arm and RISC-V development within Ashlings RiscFree IDE and Debugger.

Key Points: 
  • Ashling, a leading provider of embedded development tools, has today announced advanced support for heterogeneous multi-core Arm and RISC-V development within Ashlings RiscFree IDE and Debugger.
  • Ashling RiscFree IDE now provides the embedded development market with one toolset using a single debugger instance to program and debug any combination of Arm and RISC-V embedded devices using JTAG or Arm SWD Coresight core debug interfaces.
  • Were happy to announce RiscFree multi-core, simultaneous debug support for Arm and RISC-V powered devices developed in close co-operation with our Arm and RISC-V customers and ecosystem partners.
  • Through its close cooperation with leading semiconductor vendors, Ashling has become a leader in the Embedded Software Development Tools market.

Synopsys DesignWare CXL IP Supports AMBA CXS Protocol Targeting High-Performance Computing SoCs

Retrieved on: 
Thursday, October 8, 2020

The Synopsys CXL IP, operating at 32GT/s with 512-bit data width, supports all required CXL protocols and device types to meet specific application requirements

Key Points: 
  • The Synopsys CXL IP, operating at 32GT/s with 512-bit data width, supports all required CXL protocols and device types to meet specific application requirements
    The industry-first CXL IP complete solution encompasses configurable controller, 32GT/s PHYs in a range of FinFET processes, and verification IP
    Synopsys, Inc. (Nasdaq: SNPS)today announced that its DesignWare CXL Controller IP now supports the AMBA CXS protocol, enabling an efficient interface with the latest, highly scalable Arm Neoverse Coherent Mesh Network to provide an optimized multichip IP stack for a range of high-performance computing, datacenter, and networking system-on-chip (SoCs).
  • The DesignWare CXL Controller supports all the required CXL protocol types (.cache, .io, and .mem) and allows mixing multiple types within a single clock-cycle transfer for design flexibility.
  • Support for CXS enables the extremely low-latency, high-bandwidth DesignWare CXL IP to extend its capabilities across Arm-based SoCs requiring cache coherency and fast chip-to-chip interconnects.
  • "By providing support for the AMBA CXS protocol, designers can easily interface Synopsys' DesignWare CXL IP to the Arm Coherent Mesh Network platform to meet the high-bandwidth requirements of their data-intensive Arm-based SoC designs."

Renesas Selects Andes RISC-V 32-Bit CPU Cores for its First RISC-V Implementation of ASSPs

Retrieved on: 
Thursday, October 1, 2020

Renesas selected the AndesCore IP 32-bit RISC-V CPU cores to embed into its new application-specific standard products that will begin customer sampling in the second half of 2021.

Key Points: 
  • Renesas selected the AndesCore IP 32-bit RISC-V CPU cores to embed into its new application-specific standard products that will begin customer sampling in the second half of 2021.
  • We are thrilled that Renesas, a top-tier global MCU provider has designed Andes RISC-V cores into their pre-programmed application-specific standard products.
  • Renesas customers will benefit from a modern ISA constructed for the needs of 21st century computing.
  • In addition, an extensive network of regional Renesas partners with specialized expertise will provide cutting edge and sharply focused customer support.

Interface Masters Announces Enterprise Security Design Wins for the New Cost-Effective Tahoe 8722 Cavium® OCTEON® III Based Networking Appliance

Retrieved on: 
Thursday, October 1, 2020
Key Points: 
  • View the full release here: https://www.businesswire.com/news/home/20201001005155/en/
    Cost-Effective Tahoe 8722 1U Networking Appliance (Photo: Business Wire).
  • The Silicon Valley designed and manufactured Tahoe 8722 security appliance rounds out Interface Masters broad portfolio of Cavium OCTEON III based appliances.
  • As with all Interface Masters appliances, the device includes out-of-the-box support for the Cavium Software Development Kit (SDK) and for Linux based multi-core MIPS processor environments.
  • Based on MIPS, ARM, PowerPC, x86 processors, and switch fabrics up to 12.8T, Interface Masters appliance models enable OEMs to significantly reduce time-to-market.

Arm Accelerates the Next Generation Cloud-to-Edge Infrastructure

Retrieved on: 
Wednesday, September 23, 2020

That decade-long effort to lay the groundwork for a more efficient infrastructure was realized when we announced Arm Neoverse , a new compute platform that would deliver 30% year-over-year performance improvements through 2021.

Key Points: 
  • That decade-long effort to lay the groundwork for a more efficient infrastructure was realized when we announced Arm Neoverse , a new compute platform that would deliver 30% year-over-year performance improvements through 2021.
  • Now more than ever, Arm is focused on partnering with its ecosystem to understand the problems they are trying to solve, and delivering the high-performance, secure platforms needed to enable the infrastructure of tomorrow.
  • To accelerate this infrastructure transformation and enable new levels of innovation, Arm is announcing the next phase for Neoverse with the addition of two new platforms on its product roadmap.
  • For the first time today, Arm is introducing the Arm Neoverse V1 platform, and the Neoverse N2, the second-generation N-series platform.