Peripheral Component Interconnect

Renesas Expands Data Center Solutions Portfolio with Industry’s First CK440Q-Compliant Clock Generator for PCIe Gen5 and Beyond

Retrieved on: 
Thursday, February 4, 2021

The latest in a long line of PCIe industry firsts from Renesas, the 9SQ440 is the industrys first CK440Q-compliant server clock generator.

Key Points: 
  • The latest in a long line of PCIe industry firsts from Renesas, the 9SQ440 is the industrys first CK440Q-compliant server clock generator.
  • View the full release here: https://www.businesswire.com/news/home/20210204005428/en/
    First CK440 Clock Generator for Next-Gen Intel Server Platforms (Photo: Business Wire)
    Customers can combine the newest member of Renesas comprehensive portfolio of data center solutions with the companys broader lineup of PCIe timing solutions , including PCIe Gen5 clock buffers, and its portfolio of infrastructure power and smart power stage (SPS) devices to address their complete data center solution needs.
  • PCIe clock generators are the heart of PCIe timing and with tighter specification requirements for the latest standard, PCIe Gen5-compliant clock generators like the 9SQ440 provide significant design flexibility and margin for customers, said Bobby Matinpour, Vice President, Data Center Business Division at Renesas.
  • For more information on Renesas complete portfolio of PCIe clock timing solutions, please visit renesas.com/pcietiming .

Microchip Accelerates Machine Learning and Hyperscale Computing Infrastructure with the World’s First PCI Express® 5.0 Switches

Retrieved on: 
Tuesday, February 2, 2021

CHANDLER, Ariz., Feb. 02, 2021 (GLOBE NEWSWIRE) -- Applications such as data analytics, autonomous-driving and medical diagnostics are driving extraordinary demands for machine learning and hyperscale compute infrastructure.

Key Points: 
  • CHANDLER, Ariz., Feb. 02, 2021 (GLOBE NEWSWIRE) -- Applications such as data analytics, autonomous-driving and medical diagnostics are driving extraordinary demands for machine learning and hyperscale compute infrastructure.
  • Accelerators, graphic processing units (GPUs), central processing units (CPUs) and high-speed network adapters continue to drive the need for higher performance PCIe infrastructure.
  • Coupled with our XpressConnect family of PCIe 5.0 and Compute Express Link (CXL) 1.1/2.0 retimers, Microchip offers the industrys broadest portfolio of PCIe Gen 5 infrastructure solutions with the lowest latency and end-to-end interoperability.
  • Note: The Microchip name and logo and the Microchip logo are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

TE Connectivity's new board-to-board stacking connectors offer an economic way to upgrade COM Express applications to 16 GT/s speeds

Retrieved on: 
Thursday, January 28, 2021

These new connectors are compliant with the COM Express Type 7 specification and can be compatible with the PCIe Gen 4 protocol.

Key Points: 
  • These new connectors are compliant with the COM Express Type 7 specification and can be compatible with the PCIe Gen 4 protocol.
  • Can support up to 16 giga transmission per second (GT/s), doubling the performance of most previous COM connector generations.
  • To learn more about TE's free height stacking COM connectors, visit the stacking connectors landing page .
  • TE Connectivity, TE, TE connectivity (logo), and EVERY CONNECTION COUNTS are trademarks owned or licensed by the TE Connectivity Ltd. family of companies.

Synopsys Demonstrates Silicon Proof of DesignWare 112G Ethernet PHY IP in 5nm Process for High-Performance Computing SoCs

Retrieved on: 
Thursday, January 28, 2021

MOUNTAIN VIEW, Calif., Jan. 28, 2021 /PRNewswire/ --Synopsys, Inc. (Nasdaq: SNPS) today announced the silicon proof of DesignWare 112G Ethernet PHY IP in 5nm FinFET process, delivering significant performance, power and area advantages.

Key Points: 
  • MOUNTAIN VIEW, Calif., Jan. 28, 2021 /PRNewswire/ --Synopsys, Inc. (Nasdaq: SNPS) today announced the silicon proof of DesignWare 112G Ethernet PHY IP in 5nm FinFET process, delivering significant performance, power and area advantages.
  • DesignWare 112G Ethernet PHY is an integral part of Synopsys' comprehensive IP portfolio for high-performance cloud computing applications, including widely used protocols such as PCI Express, DDR, HBM, Die-to-Die, CXL and CCIX.
  • "The comprehensive DesignWare 112G Ethernet PHY IP solution in 5nm FinFET process with differentiated performance, power and area enables designers to significantly reduce their integration risk for a faster path to silicon success."
  • To accelerate prototyping, software development and integration of IP into SoCs, Synopsys' IP Accelerated initiative offers IP prototyping kits, IP software development kits, and IP subsystems.

Synopsys Delivers Industry's First Integrity and Data Encryption Security IP Modules for PCI Express 5.0 and Compute Express Link 2.0 Specifications

Retrieved on: 
Wednesday, January 27, 2021

"By offering the unique combination of interface and security IP for the PCIe 5.0 specification, Synopsys is enabling the design community to quickly implement necessary security functionality into their systems."

Key Points: 
  • "By offering the unique combination of interface and security IP for the PCIe 5.0 specification, Synopsys is enabling the design community to quickly implement necessary security functionality into their systems."
  • DesignWare IDE Security IP Modules for PCI Express 5.0 architecture and CXL 2.0 are available now.
  • The broad Synopsys DesignWare IP portfolio includes logic libraries, embedded memories, embedded test, analog IP, wired and wireless interface IP, security IP, embedded processors, and subsystems.
  • To accelerate prototyping, software development and integration of IP into SoCs, Synopsys' IP Accelerated initiative offers IP prototyping kits, IP software development kits and IP subsystems.

Flex Logix Pairs its InferX X1 AI Inference Accelerator with the High-Bandwidth Winbond 4Gb LPDDR4X Chip to Set a New Benchmark in Edge AI Performance

Retrieved on: 
Wednesday, January 27, 2021

The Winbond LPDDR4X chip is being paired with Flex Logix's InferXX1 edge inference accelerator chip, which is based on an innovative architecture that features arrays of reconfigurable Tensor Processors.

Key Points: 
  • The Winbond LPDDR4X chip is being paired with Flex Logix's InferXX1 edge inference accelerator chip, which is based on an innovative architecture that features arrays of reconfigurable Tensor Processors.
  • "The price/performance advantage of using InferX with our LPDDR4X chip has the potential to significantly expand AI applications by finally bringing inference capabilities to the mass market."
  • The Winbond LPDDR4X chip operates alongside the InferX X1 processor in Flex Logix's half-height/half-length PCIe embedded processor board for edge servers and gateways.
  • Dana McCarty, VP of Sales & Marketing for Flex Logix's AI Inference Products said: "The combination of the unique InferX X1 processor and Winbond's high-bandwidth LPDDR4X chip sets a new benchmark in edge AI performance.

MagicCube is First Startup Appointed to PCI Security Standards Council 2021-2022 Board of Advisors

Retrieved on: 
Monday, January 25, 2021

The Board of Advisors represents PCI SSC Participating Organizations worldwide to ensure global industry involvement in the development of PCI Security Standards and programs.

Key Points: 
  • The Board of Advisors represents PCI SSC Participating Organizations worldwide to ensure global industry involvement in the development of PCI Security Standards and programs.
  • "The Board of Advisors provides industry expertise and perspectives that influence and shape the development of PCI Security Standards and programs," said Lance J. Johnson, PCI SSC Executive Director.
  • MagicCube is one of 31 board members to join the PCI Security Standards Council in its efforts to secure payment data globally.
  • "We're extremely proud to have been elected to join the PCI Security Standards Council's Board of Advisors to continue our work on advising in the development of the PCI Security Standards," said Nancy Zayed, CTO of MagicCube.

Avery Design Announces CXL™ 2.0 VIP

Retrieved on: 
Friday, January 22, 2021

Additional VIPs supporting key SoC interface protocols CPI, CXS, LPIF

Key Points: 
  • Additional VIPs supporting key SoC interface protocols CPI, CXS, LPIF
    Dynamic configuration of VIP for legacy PCIe, CXL 2.0 or CXL 1.1 including CXL device types 1-3
    Realistic traffic arbitration among CXL.IO, CXL.Cache, CXL.Mem and CXL control packets.
  • Our collaboration with Avery has been very fruitful in making sure that our CXL design IP (COMPEX) is fully verified and compliant to the CXL specifications, said Ravi Thummarukudy, CEO of Mobiveil.
  • Verifying COMPEX with Avery VIP enabled us to successfully validate it with Intels CXL host platform quickly.
  • Avery has been on the leading edge when it comes to delivering the latest Industry compliant VIP solutions such as CXL, PCIe and NVMe etc.

ADLINK Introduces a Portable PXI Express Chassis with Fast, Versatile Thunderbolt™ 3 Interfaces

Retrieved on: 
Thursday, January 21, 2021

ADLINK Technology Inc. , a global leader in edge computing, has introduced the PXES-2314T , a new generation PXI Express chassis with versatile, high bandwidth Thunderbolt 3 interfaces.

Key Points: 
  • ADLINK Technology Inc. , a global leader in edge computing, has introduced the PXES-2314T , a new generation PXI Express chassis with versatile, high bandwidth Thunderbolt 3 interfaces.
  • "Previously, a typical PXI bridge setup required a desktop expansion card, chassis module, and connecting cable, severely limiting portability.
  • The chassis offers four PXI Express Hybrid slots: two PXIe Hybrid slots up to PCIe Gen2 x1 and two PXIe Hybrid slots up to PCIe Gen3 x4.
  • The 4-slot PXES-2314T adds a portable test and measurement solution to complement ADLINK's existing 6-,9-, and 18-slot high-density chassis.

PLDA Announces XpressLINK-SOC™ CXL Controller IP with Support for the AMBA CXS Issue B Protocol

Retrieved on: 
Tuesday, January 19, 2021

PLDA, the industry leader in high-speed interconnect solutions, today announced that PLDAs industry-leading XpressLINK-SOC CXL IP provides full support for the AMBA CXS Issue B (CXS-B) interface protocol.

Key Points: 
  • PLDA, the industry leader in high-speed interconnect solutions, today announced that PLDAs industry-leading XpressLINK-SOC CXL IP provides full support for the AMBA CXS Issue B (CXS-B) interface protocol.
  • AMBA CXS is a credit-based streaming protocol that enables high-bandwidth transmission of packets between a user application and the protocol controller.
  • Using a CXS interface, the designer can bypass the controllers transaction layer, which can significantly reduce latency.
  • The CXS specification defines the interface between an on-chip interconnect, such as the Arm CoreLink Coherent Mesh Network, and a PCIe or CXL controller to optimize transport of CCIX and CXL packets.