Arm, Cadence and Xilinx Introduce First Arm Neoverse System Development Platform for Next-Generation Cloud-to-Edge Infrastructure, Implemented on TSMC 7nm Process Technology
The Neoverse N1 SDP was developed jointly by Arm, Cadence and Xilinx on TSMCs process technology, and includes Cadence IP for CCIX, PCI Express (PCIe) Gen 4 and DDR4 PHY IP.
- The Neoverse N1 SDP was developed jointly by Arm, Cadence and Xilinx on TSMCs process technology, and includes Cadence IP for CCIX, PCI Express (PCIe) Gen 4 and DDR4 PHY IP.
- The Neoverse N1 SDP will be available in limited quantities in Q2 2019 with wider availability in subsequent quarters.
- Our ongoing SDP collaboration with Cadence, TSMC, and Xilinx truly enables developers with the system development tools necessary to innovate and deliver optimized Neoverse-based designs.
- Arm and Neoverse are registered trademarks or trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.