Electronic engineering

Firecomms Collaborates with Egrtech in Developing Highly Efficient Silicon Carbide (SiC) Gate Drivers

Retrieved on: 
Monday, April 29, 2019

Firecomms RedLink transceivers and Plastic Optical Fibre (POF) provide galvanic isolation on the data control lines of Egrtech's EGDR-90 SiC gate driver board.

Key Points: 
  • Firecomms RedLink transceivers and Plastic Optical Fibre (POF) provide galvanic isolation on the data control lines of Egrtech's EGDR-90 SiC gate driver board.
  • Furthermore, a high dV/dt immunity is achieved by the integration of a plug-on POF module using Firecomms RedLink 5 Mbd dual voltage transceivers.
  • "The increased power density of SiC gate drivers result in significantly higher EMI compared to traditional IGBT solutions.
  • The company is able to provide schematic, PCB layout (Altium Designer), software code, power simulation (PSIM) based on customer requirements.

GE Aviation and Auterion Team to Provide All-in-One Hardware and Software Platform for Commercial Drones

Retrieved on: 
Monday, April 29, 2019

Today, GE Aviation and Auterion announce the integration of the Auterion Enterprise PX4 operating system on GE Aviations Unmanned Aircraft System avionics platform.

Key Points: 
  • Today, GE Aviation and Auterion announce the integration of the Auterion Enterprise PX4 operating system on GE Aviations Unmanned Aircraft System avionics platform.
  • GE Aviation is providing the avionics hardware, application computing, flight management and integration into airframes.
  • Flight testing of the hardware and software platform took place over the last three weeks at Reno-Stead airport in Reno, Nevada.
  • The hardware and software platform is designed with commercial vehicle original equipment manufacturers (OEMs) and/or service providers in mind.

New Balluff BMPs combine IO-Link, Analog in Single Device

Retrieved on: 
Friday, April 26, 2019

FLORENCE, Ky., April 26, 2019 /PRNewswire-PRWeb/ -- The latest additions to the Balluff BMP family of magnetic position sensors combine IO-Link, analog voltage and analog current in a singular device to overcome the limitations of discrete pneumatic cylinder switches.

Key Points: 
  • FLORENCE, Ky., April 26, 2019 /PRNewswire-PRWeb/ -- The latest additions to the Balluff BMP family of magnetic position sensors combine IO-Link, analog voltage and analog current in a singular device to overcome the limitations of discrete pneumatic cylinder switches.
  • The BMP magnetic position sensors calculate the actual target position of the magnet and output it as a position-dependent analog or IO-Link signal.
  • Founded in Neuhausen auf den Fildern in 1921, Balluff now employees 3600 workers in distribution, production and development sites around the globe.
  • This guarantees excellent worldwide product availability for our customers, as well as high-quality consulting and service directly on site.

Xilinx Reports Record Revenues Exceeding $3 Billion For Fiscal 2019

Retrieved on: 
Wednesday, April 24, 2019

The webcast and subsequent replay will be available in the investor relations section of the Company's web site at www.investor.xilinx.com .

Key Points: 
  • The webcast and subsequent replay will be available in the investor relations section of the Company's web site at www.investor.xilinx.com .
  • Fiscal fourth quarter 2019 results and business outlook for the June quarter include financial measures which are not determined in accordance with the United States generally accepted accounting principles (GAAP), as indicated.
  • Non-GAAP measures should not be considered as a substitute for, or superior to, financial measures determined in accordance with GAAP.
  • Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, Vivado, Alveo, Versal and other designated brands included herein are trademarks of Xilinx in the United States and other countries.

R. Iris Bahar to Receive Marie R. Pistilli Women in Engineering Achievement Award

Retrieved on: 
Wednesday, April 24, 2019

Iris Bahar, Professor of Engineering and Computer Science at Brown University, has been selected as the 2019 recipient of the Marie R. Pistilli Women in Electronic Design Award , a prestigious annual honor that recognizes individuals who have significantly helped to advance women in electronic design.

Key Points: 
  • Iris Bahar, Professor of Engineering and Computer Science at Brown University, has been selected as the 2019 recipient of the Marie R. Pistilli Women in Electronic Design Award , a prestigious annual honor that recognizes individuals who have significantly helped to advance women in electronic design.
  • The award is named for the late Marie R. Pistilli, former co-founder of DAC, who placed a high value on equality, diversity, and acceptance.
  • Given Iris technical contributions to the field of EDA and her dedication to the goal of advancing the status of women in electronic design, I cannot think of a more deserving recipient for the 2019 Marie R. Pistilli Women in Electronic Design Achievement Award.
  • The award is named for DACs former organizer, the late Marie Pistilli, who worked hard to further the advancement of women in engineering.

Outlook on the Worldwide Microdisplays Market, 2026 - OLED Technology Expected to Be the Fastest Growing Segment

Retrieved on: 
Wednesday, April 24, 2019

The global market for microdisplays is expected to cross US$ 4,250.5 million, growing at a CAGR of 22.5% throughout the forecast period.

Key Points: 
  • The global market for microdisplays is expected to cross US$ 4,250.5 million, growing at a CAGR of 22.5% throughout the forecast period.
  • In addition, technological developments in microdisplays in order to meet high resolutions demand of potential applications expected to fuel the growth of microdisplays throughout the forecast period from 2018 to 2026.
  • OLED technology is expected to be the fastest growing segment compared to other technologies due to its benefits such as of low power consumption and fewer chances of failure.
  • OLED technology is expected to witness the considerable growth in the near future, with continuous advancements in technology and declining prices of this technology.

ANSYS Achieves Certification for TSMC's Innovative System-on-Integrated-Chips (TSMC-SoIC™) Advanced 3D Chip Stacking Technology

Retrieved on: 
Wednesday, April 24, 2019

In addition to SoIC certification, TSMC validated the reference flow for the latest Chip-on-Wafer-on-Substrate (CoWoS) packaging technology using ANSYS RedHawk, ANSYS RedHawk-CTA, ANSYSCMAand ANSYSCSMand their corresponding chip models for system level analysis.

Key Points: 
  • In addition to SoIC certification, TSMC validated the reference flow for the latest Chip-on-Wafer-on-Substrate (CoWoS) packaging technology using ANSYS RedHawk, ANSYS RedHawk-CTA, ANSYSCMAand ANSYSCSMand their corresponding chip models for system level analysis.
  • "The collaborative efforts combining ANSYS' comprehensive chip-package co-analysis solutions with TSMC SoIC advanced chip stacking technology address complex multiphysics challenges in 3D-IC packaging technologies."
  • "ANSYS' comprehensive chip aware system and system aware chip signoff solutions empower mutual customers to accelerate design convergence with greater confidence."
  • Through ourstrategyof Pervasive Engineering Simulation, we help the world's most innovative companies deliver radically better products to their customers.

Synopsys Design Platform Certified for TSMC's Innovative SoIC Chip Stacking Technology

Retrieved on: 
Tuesday, April 23, 2019

Solution includes multi-die layout implementation, as well as parasitic extraction and timing analysis coupled with physical verification

Key Points: 
  • Solution includes multi-die layout implementation, as well as parasitic extraction and timing analysis coupled with physical verification
    Collaborating with early partners to accelerate their highly integrated, next-generation products to market
    Synopsys, Inc. (Nasdaq:SNPS) today announced that the Synopsys Design Platform has been certified for TSMC's latest System-on-Integrated-Chips (TSMC-SoIC) 3D chip stacking technology.
  • Key products and features of the Synopsys Design Platform supporting TSMC's advanced SoIC chip stacking technology include:
    IC Compiler II place-and-route: Efficient design capture and flexible planning of high-complexity multi-die ICs.
  • "Our ongoing collaboration with Synopsys results in delivering scalable methodologies for TSMC's innovative SoIC advanced chip stacking technology.
  • "Synopsys' digital design platform and the co-developed associated methodologies will allow designers to confidently meet their schedules when deploying these next-generation, multi-die solutions."

ADAS and Autonomous Driving Industry Chain Report, 2018-2019- Automotive Processor and Computing Chip

Retrieved on: 
Tuesday, April 23, 2019

That's because an automotive processor also has to consider how much power is consumed, how much computing power is used or whether it is up to the automotive and safety standards or not.

Key Points: 
  • That's because an automotive processor also has to consider how much power is consumed, how much computing power is used or whether it is up to the automotive and safety standards or not.
  • Automotive processor, also referred to as automotive computing chip, typically falls into three types: Application specific standard products (ASSP), like CPU and GPU; application specific integrated circuits (ASIC); field programmable gate arrays (FPGA).
  • And conforming to the active safety standards poses a bigger challenge to development of automotive computing chip tool chain.
  • In China, Horizon Robotics, an autonomous driving chip bellwether, provides full-stack perception software and full-stack tool chain.

Cadence Design Solutions Certified for TSMC-SoIC™ Advanced 3D Chip Stacking Technology

Retrieved on: 
Tuesday, April 23, 2019

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced TSMC certified Cadences design solutions for the new TSMC System-on-Integrated-Chips (TSMC-SoIC) 3D advanced chip stacking technology, which integrates heterogeneous chipsincluding logic ICs and memorythat are fabricated on different process nodes onto a single chip stack for a subsequent packaging process.

Key Points: 
  • Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced TSMC certified Cadences design solutions for the new TSMC System-on-Integrated-Chips (TSMC-SoIC) 3D advanced chip stacking technology, which integrates heterogeneous chipsincluding logic ICs and memorythat are fabricated on different process nodes onto a single chip stack for a subsequent packaging process.
  • For more information on the Cadence solutions that support the TSMC-SoIC advanced packaging technology, visit www.cadence.com/go/soic .
  • The Cadence tools, reference flows and methodologies for our new SoIC advanced chip stacking technology complement our well-established InFO, WoW and CoWoS chip integration solutions, providing customers with even more flexibility to integrate multiple die onto a single device using 3D stacking techniques, said Suk Lee, TSMC senior director, Design Infrastructure Management Division.
  • Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.