eSilicon to debut AI Accelerator software and a new chiplet model at Hot Chips 2019

eSilicons new AI Accelerator maps high-level AI workloads to the neuASIC platform and estimates PPA (power, performance, area) for the algorithm in the resultant silicon implementation.

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Articles, Electronic engineering, Computing, Application-specific integrated circuits, Fabless semiconductor companies, Computer optimization, eSilicon, AI accelerator, Computational neuroscience, Artificial intelligence, Accelerator, Articles, Electronic engineering, Computing, Application-specific integrated circuits, Fabless semiconductor companies, Computer optimization, eSilicon, AI accelerator, Computational neuroscience, Artificial intelligence, Accelerator
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SAN JOSE, Us
Organisation: 
ESILICON CORPORATION
Summary
Key Points: 
  • eSilicons new AI Accelerator maps high-level AI workloads to the neuASIC platform and estimates PPA (power, performance, area) for the algorithm in the resultant silicon implementation.
  • neuASIC IP plus the AI Accelerator software allow design exploration of candidate architectures to ensure the design will be within the target specifications.
  • eSilicon will be demonstrating AI Accelerator on Monday and Tuesday at its sponsor table.
  • AI Accelerator is available in IP Navigator, eSilicons IP exploration and evaluation tool, at no charge.



New software maps high-level AI workloads to eSilicon’s neuASIC modular AI ASIC IP platform

SAN JOSE, Calif., Aug. 15, 2019 (GLOBE NEWSWIRE) --

What
eSilicon, an independent provider of FinFET-class ASIC design, market-specific IP platforms and advanced 2.5D packaging solutions, will exhibit at Hot Chips 31.

eSilicon at Hot Chips 31
Introducing AI Accelerator Software
eSilicon’s 7nm FinFET neuASIC™ AI IP platform is a library of AI-specific tiles that can be configured to support an AI algorithm. eSilicon’s new AI Accelerator maps high-level AI workloads to the neuASIC platform and estimates PPA (power, performance, area) for the algorithm in the resultant silicon implementation.

neuASIC IP plus the AI Accelerator software allow design exploration of candidate architectures to ensure the design will be within the target specifications. This approach supports changes to the algorithm or the package.

eSilicon will be demonstrating AI Accelerator on Monday and Tuesday at its sponsor table.

AI Accelerator is available in IP Navigator, eSilicon’s IP exploration and evaluation tool, at no charge. A free eSilicon STAR account is required to access Navigator, which may be requested here.

Update on Chiplets
The idea of chiplets makes sense in terms of yield, cost and risk, but they haven’t really caught on. Is there a chiplet business model that works?

When & Where
Sunday-Tuesday, August 18-20, 2019
Memorial Auditorium, Stanford Campus
Palo Alto, California

Registration for the conference is still open online or on site during the event at the registration booth.

About eSilicon
eSilicon provides complex FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC-proven, differentiating IP includes highly configurable 7nm 56G/112G SerDes plus networking-optimized 16/14/7nm FinFET IP platforms featuring HBM2 PHY, TCAM, specialized memory compilers and I/O libraries. Our neuASIC platform provides AI-specific IP and a modular design methodology to create adaptable, highly efficient AI ASICs. eSilicon serves the high-bandwidth networking, high-performance computing, AI and 5G infrastructure markets. www.esilicon.com

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eSilicon is a registered trademark, and neuASIC and the eSilicon logo are trademarks, of eSilicon Corporation. Other trademarks are the property of their respective owners. 

Contacts:  
Sally Slemons Nanette Collins
eSilicon Corporation Public Relations for eSilicon
[email protected] [email protected]


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